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Conventional negative\u2010capacitance FETs (NC\u2010FETs) are designed to suppress ferroelectric bistability to enable hysteresis\u2010free sub\u2010thermionic switching, whereas ferroelectric FETs (Fe\u2010FETs) exploit bistable polarization to provide non\u2010volatile memory, leaving the two operating regimes largely separate in practice. Here, we report a van der Waals ferroelectric negative\u2010capacitance transistor (FeNC\u2010FET) that simultaneously realizes stabilized negative capacitance and intrinsic bistable polarization by employing a CIPS\/h\u2010BN\/\u03b1\u2010In\n                    <jats:sub>2<\/jats:sub>\n                    Se\n                    <jats:sub>3<\/jats:sub>\n                    trilayer gate stack. Landau\u2013Khalatnikov analysis and polarization\u2013voltage measurements confirm complementary ferroelectric roles in which CIPS provides static negative curvature, h\u2010BN enables charge compensation, and \u03b1\u2010In\n                    <jats:sub>2<\/jats:sub>\n                    Se\n                    <jats:sub>3<\/jats:sub>\n                    supplies non\u2010volatile polarization. This cooperative mechanism enables steep sub\u2010threshold swings of 35\u00a0mV\/dec (forward) and 51\u00a0mV\/dec (reverse), a \u223c3\u00a0V memory window, long retention (&gt;10\n                    <jats:sup>4<\/jats:sup>\n                    s), and endurance exceeding 2500 cycles. The device further performs AND, OR, and majority logic\u2010in\u2010memory operations using 10 \u00b5s pulses with clear ON\/OFF separation. These results establish the FeNC\u2010FET as a compact platform that combines steep\u2010slope switching with non\u2010volatile programmability in a single device, enabling low\u2010bias readout, short\u2010pulse programming, and robust logic\u2010in\u2010memory operation.\n                  <\/jats:p>","DOI":"10.1002\/smll.202514878","type":"journal-article","created":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T09:13:02Z","timestamp":1778663582000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Unified Steep\u2010Slope Switching and Non\u2010Volatile Memory in a Complementarily Stabilized van der Waals Ferroelectric Transistor"],"prefix":"10.1002","volume":"22","author":[{"given":"Sangmin","family":"Lee","sequence":"first","affiliation":[{"name":"SKKU Advanced Institute of Nanotechnology (SAINT) Sungkyunkwan University  Suwon South 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