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Conventional R\u2010FETs, however, rely on a single gating mechanism, which forces a trade\u2010off between nonvolatile logic reconfiguration and analog synaptic operation. Here, we report a hybrid\u2010gate R\u2010FET that combines floating\u2010gate (FG) and ferroelectric (FE) operation within a single van der Waals gate stack of MoTe\n                    <jats:sub>2<\/jats:sub>\n                    ,\n                    <jats:italic>h<\/jats:italic>\n                    \u2010BN, and In\n                    <jats:sub>2<\/jats:sub>\n                    Se\n                    <jats:sub>3<\/jats:sub>\n                    . In the FG mode, stored charge strongly dopes the ambipolar MoTe\n                    <jats:sub>2<\/jats:sub>\n                    channel, giving stable reconfiguration among insulating, metallic, n\u2010FET, and p\u2010FET states. On this basis, the device reconfigures into inverter and switch operation and, through circuit\u2010level simulation, into six Boolean logic gates within one layout. In the FE mode, polarization switching modulates the channel conductance at low energy, yielding 6\u2010bit synaptic states over a dynamic range of about 100. A hardware\u2010level spiking neural network built on the experimentally measured synaptic characteristics reaches about 90% accuracy on the MNIST dataset in a MATLAB\u2010based simulation. The hybrid\u2010gate R\u2010FET thus provides a versatile device platform that integrates two distinct gating mechanisms and selectively exploits their respective advantages for reconfigurable logic and neuromorphic computing.\n                  <\/jats:p>","DOI":"10.1002\/smll.76064","type":"journal-article","created":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T04:39:44Z","timestamp":1790829584000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Van der Waals Hybrid\u2010Gate Reconfigurable Transistor Integrating Floating\u2010Gate Logic and Ferroelectric Synaptic Functions"],"prefix":"10.1002","author":[{"given":"Hyeonchang","family":"Son","sequence":"first","affiliation":[{"name":"School of Electrical Engineering and Computer Science (EECS) Gwangju Institute of Science and Technology (GIST)  Gwangju Republic of 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Gwangju Institute of Science and Technology (GIST)  Gwangju Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gwangmin","family":"Yu","sequence":"additional","affiliation":[{"name":"Department of Mechanical Engineering Korea Advanced Institute of Science and Technology (KAIST)  Daejeon Republic of Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7676-8938","authenticated-orcid":false,"given":"Dongseok","family":"Kwon","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering and Computer Science (EECS) Gwangju Institute of Science and Technology (GIST)  Gwangju Republic of Korea"},{"name":"Department of Semiconductor Engineering Gwangju Institute of Science and Technology (GIST)  Gwangju Republic of Korea"},{"name":"Graduate School of Advanced Semiconductor Engineering Gwangju Institute of Science and Technology (GIST)  Gwangju Republic of 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