{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T16:46:21Z","timestamp":1725468381963},"publisher-location":"Boston","reference-count":13,"publisher":"Kluwer Academic Publishers","isbn-type":[{"type":"print","value":"0387334025"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/0-387-33403-3_15","type":"book-chapter","created":{"date-parts":[[2006,8,15]],"date-time":"2006-08-15T18:25:16Z","timestamp":1155666316000},"page":"229-245","source":"Crossref","is-referenced-by-count":1,"title":["Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes"],"prefix":"10.1007","author":[{"given":"Stephan","family":"Henzler","sequence":"first","affiliation":[]},{"given":"Philip","family":"Teichmann","sequence":"additional","affiliation":[]},{"given":"Markus","family":"Koban","sequence":"additional","affiliation":[]},{"given":"J\u00f6rg","family":"Berthold","sequence":"additional","affiliation":[]},{"given":"Georg","family":"Georgakos","sequence":"additional","affiliation":[]},{"given":"Doris","family":"Schmitt-Landsiedel","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"15_CR1","unstructured":"K-S. Min, H. Kawaguchi, T. Sakurai et al., Zigzag Super Cut-off CMOS Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era, ISSCC 2003"},{"key":"15_CR2","unstructured":"R.K. Krishnamurthy, A. Alvandpour, S. Mathew, M. Anders, V. De, S. Borkar et al., High-performance, Low-power, and Leakage-tolerance Challenges for Sub-70nm Microprocessor Circuits\u201d, ESSCIRC (2002)"},{"key":"15_CR3","doi-asserted-by":"crossref","unstructured":"S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada et al., 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, JSSC, 30(8) (1995)","DOI":"10.1109\/4.400426"},{"key":"15_CR4","doi-asserted-by":"crossref","unstructured":"B. Calhoun, F. Honor\u00e9, A. Chandrakasan, A Leakage Reduction Methodology for Distributed MTCMOS, JSSC 39(5) (2004)","DOI":"10.1109\/JSSC.2004.826335"},{"issue":"11","key":"15_CR5","first-page":"1838","volume":"38","author":"J. Tschanz","year":"2003","unstructured":"J. Tschanz, S. Narendra et al., Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors, JSSC 38(11) 1838\u20131845 (2003)","journal-title":"JSSC"},{"issue":"10","key":"15_CR6","first-page":"1498","volume":"35","author":"H. Kawaguchi","year":"2000","unstructured":"H. Kawaguchi, K. Nose, T. Sakurai, A Super Cut-Off (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current, JSSC 35(10) 1498\u20131501 (2000)","journal-title":"JSSC"},{"key":"15_CR7","unstructured":"S.I.A., ITRS, International Technology Roadmap for Semiconductors, 2002"},{"key":"15_CR8","doi-asserted-by":"crossref","unstructured":"J. Kao, A. Chandrakasan, D. Antoniadis, Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology, DAC (1997)","DOI":"10.1145\/266021.266182"},{"key":"15_CR9","doi-asserted-by":"crossref","unstructured":"St. Henzler, G. Georgakos, J. Berthold, D. Schmitt-Landsiedel, Two Level Compact Simulation Methodology For Timing Analysis Of Power-Switched Circuits, PATMOS 789\u2013798, (2004).","DOI":"10.1007\/978-3-540-30205-6_81"},{"key":"15_CR10","doi-asserted-by":"crossref","unstructured":"W-C. Lee, C. Hu et al., Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction-and Valence-Band Electron and Hole Tunneling, IEEE Transactions on Electron Devices, 48(7), (2001)","DOI":"10.1109\/16.930653"},{"key":"15_CR11","unstructured":"J.W. Fattaruso, Buss et al., Current Trends in analog Design, Short Course on System-on-a-Chip, ISSCC 2003"},{"key":"15_CR12","unstructured":"M. Drazdziulis, P. Larsson-Edefors et al., A Power Cut-Off Technique for Gate Leakage Suppression, ESSCIRC (2004)"},{"issue":"2","key":"15_CR13","doi-asserted-by":"publisher","first-page":"103","DOI":"10.1049\/el:20040088","volume":"40","author":"St. Henzler","year":"2004","unstructured":"St. Henzler, G. Georgakos, J. Berthold, D. Schmitt-Landsiedel, A Fast Power-Efficient Circuit-Block Switch-Off Scheme, IEE Electronics Letters, 40(2) 103\u2013104, (2004)","journal-title":"IEE Electronics Letters"}],"container-title":["IFIP International Federation for Information Processing","VLSI-SOC: From Systems to Chips"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/0-387-33403-3_15.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T20:17:18Z","timestamp":1605644238000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/0-387-33403-3_15"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["0387334025"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/0-387-33403-3_15","relation":{},"subject":[]}}