{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T16:46:17Z","timestamp":1725468377703},"publisher-location":"Boston","reference-count":20,"publisher":"Kluwer Academic Publishers","isbn-type":[{"type":"print","value":"0387334025"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/0-387-33403-3_6","type":"book-chapter","created":{"date-parts":[[2006,8,15]],"date-time":"2006-08-15T18:25:16Z","timestamp":1155666316000},"page":"85-100","source":"Crossref","is-referenced-by-count":3,"title":["Validation of Asynchronous Circuit Specifications Using IF\/CADP"],"prefix":"10.1007","author":[{"given":"Dominique","family":"Borrione","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Menouer","family":"Boubekeur","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laurent","family":"Mounier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marc","family":"Renaudin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antoine","family":"Siriani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"1\u20132","key":"6_CR1","doi-asserted-by":"publisher","first-page":"133","DOI":"10.1016\/S0167-9317(00)80065-9","volume":"54","author":"M. Renaudin","year":"2000","unstructured":"M. Renaudin, \u201cAsynchronous Circuits and Systems: a promising design alternative\u201d, Microelectronics-Engineering Journal, Elsevier Science, Vol. 54, No 1\u20132, Dec 2000, pp. 133\u2013149.","journal-title":"Microelectronics-Engineering Journal, Elsevier Science"},{"key":"6_CR2","unstructured":"A.J. Martin, \u201cProgramming in VLSI: from communicating processes to delay-insensitive circuits\u201d, in C.A.R. Hoare, editor, Developments in Concurrency and Communication, UT Year of Programming Series, 1990, Addison-Wesley, p. 1\u201364."},{"key":"6_CR3","doi-asserted-by":"crossref","unstructured":"H. Zheng, E. Mercer, and C. Myers, \u201cAutomatic abstraction for verification of timed circuits and systems\u201d, Proc. CAV\u201901, LNCS 2102, Springer, pp. 182\u2013193, July, 2001.","DOI":"10.1007\/3-540-44585-4_16"},{"key":"6_CR4","doi-asserted-by":"crossref","unstructured":"A. Cerone, G. Milne: \u201cA Methodology for the Formal Analysis of Asynchronous Micropipelines\u201d, Proc. FMCAD 2000, LNCS No 1954, Springer Verlag, pp.246\u2013262","DOI":"10.1007\/3-540-40922-X_16"},{"key":"6_CR5","doi-asserted-by":"crossref","unstructured":"D. Borrione et al. \u201cAn Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow\u201d. Proc. 36th Hawai Int. Conf. on System Sciences (HICSS\u201903). Jan. 2003","DOI":"10.1109\/HICSS.2003.1174811"},{"key":"6_CR6","doi-asserted-by":"crossref","unstructured":"G. Delzanno and A. Podelski, \u201cModel Checking in CLP\u201d. Proc. 5th Int. Conf. TACAS\u201999. R. Cleaveland, ed., Springer Verlag LNCS No 1579, pp.223\u2013239, 1999.","DOI":"10.1007\/3-540-49059-0_16"},{"key":"6_CR7","unstructured":"http:\/\/www.inrialpes.fr\/vasy\/caclp\/"},{"key":"6_CR8","unstructured":"J. Cortadella et al. \u201cPetrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers.\u201d IEICE Trans. on Information and Systems, E80-D(3): 315\u2013325, Mar. 97."},{"key":"6_CR9","doi-asserted-by":"crossref","unstructured":"K. Van Berkel, \u201cHandshake Circuits \u2014 An Asynchronous Architecture for VLSI Programming\u201d, Cambridge University Press, 1993, ISBN: 0-521-45254-6","DOI":"10.1017\/CBO9780511585777"},{"key":"6_CR10","doi-asserted-by":"crossref","unstructured":"M. Bozga, J.-C. Fernandez, et al. \u201cIF: An Intermediate Representation and Validation Environment for Timed Asynchronous Systems\u201d. Proc. FM\u201999, Toulouse, LNCS, 1999.","DOI":"10.1007\/3-540-48119-2_19"},{"key":"6_CR11","doi-asserted-by":"crossref","unstructured":"M. Bozga, H. Jianmin, O. Maler, S. Yovine, \u201cVerification of Asynchronous Circuits using Timed Automata\u201d, Proc. TPTS\u201902 Workshop, Elsevier Science Pub. April 2002.","DOI":"10.1016\/S1571-0661(04)80468-7"},{"key":"6_CR12","unstructured":"A Dinh Duc, L. Fesquet, M. Renaudin, \u201cSynthesis of QDI Asynchronous Circuits from DTL-style Petri-Net\u201d, IEEE\/ACM Int. Workshop on Logic & Synthesis, New Orleans, June 4\u20137, 02."},{"key":"6_CR13","doi-asserted-by":"crossref","unstructured":"A. Kondratyev, J. Cortadella, M. Kishinevsky, et al.: \u201cChecking signal transition graph implementability by symbolic bdd traversal\u201d. Proc. EDTC\u201995, pp 325\u2013332, Paris, March 95.","DOI":"10.1109\/EDTC.1995.470376"},{"key":"6_CR14","unstructured":"M. Renaudin, J.B. Rigaud, A. Dinhduc, A. Rezzag, A. Sirianni, J. Fragoso: \u201cTAST CAD Tools\u201d, ASYNC\u201902 TUTORIAL, ISRN: TIMA-RR-02\/04\/01-FR, 2002"},{"key":"6_CR15","unstructured":"R. Manohar, T.K. Lee, A.J. Martin. \u201cProjection: a synthesis technique for concurrent systems\u201d. 5th Int. Symp. Advanced. Research in Asynchronous Circuits and Systems, Apr. 99."},{"key":"6_CR16","doi-asserted-by":"crossref","unstructured":"V. Khomenko and M. Koutny: \u201cTowards An Efficient Algorithm for Unfolding Petri Nets\u201d. Proc. CONCUR\u201901. Springer-Verlag, LNCS No 2154 (2001) 366\u2013380.","DOI":"10.1007\/3-540-44685-0_25"},{"key":"6_CR17","volume-title":"LOTOS-based Verification of Asynchronous Circuits","author":"M. Yoeli","year":"2001","unstructured":"M. Yoeli and A. Ginzburg, \u201cLOTOS-based Verification of Asynchronous Circuits\u201d, Tech. Report, Dept. of Computer Science, Technion, Haifa, 2001."},{"key":"6_CR18","doi-asserted-by":"crossref","unstructured":"M. Bozga et al. \u201cAutomated validation of distributed software using the IF environment\u201d, Proc. Workshop on Software Model-checking, El. Notes in TCS vol. 55 Elsevier Science Pub. July 00.","DOI":"10.1109\/NCA.2001.962542"},{"key":"6_CR19","unstructured":"http:\/\/www.agedis.de and http:\/\/www-omega.imag.fr"},{"key":"6_CR20","unstructured":"NIST, Data Encryption Standard (DES), FIPS PUB 46-3, National Institute of Standards and Technology, Reaffirmed 1999 October 25. http:\/\/csrc.nist.gov\/csrc\/fedstandards.html"}],"container-title":["IFIP International Federation for Information Processing","VLSI-SOC: From Systems to Chips"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/0-387-33403-3_6.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T20:17:20Z","timestamp":1605644240000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/0-387-33403-3_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["0387334025"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/0-387-33403-3_6","relation":{},"subject":[]}}