{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:38:17Z","timestamp":1725471497693},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540662280"},{"type":"electronic","value":"9783540485162"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1999]]},"DOI":"10.1007\/10703040_41","type":"book-chapter","created":{"date-parts":[[2006,10,9]],"date-time":"2006-10-09T14:35:59Z","timestamp":1160404559000},"page":"548-560","source":"Crossref","is-referenced-by-count":3,"title":["An ISA Comparison Between Superscalar and Vector Processors"],"prefix":"10.1007","author":[{"given":"Francisca","family":"Quintana","sequence":"first","affiliation":[]},{"given":"Roger","family":"Espasa","sequence":"additional","affiliation":[]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"41_CR1","doi-asserted-by":"publisher","first-page":"237","DOI":"10.1109\/HPCA.1997.569677","volume-title":"Third International Symposium on High-Performance Computer Architecture","author":"R. Espasa","year":"1997","unstructured":"Espasa, R., Valero, M.: Multithreaded Vector Architectures. In: Third International Symposium on High-Performance Computer Architecture, pp. 237\u2013249. IEEE Computer Society Press, San Antonio (1997)"},{"key":"41_CR2","doi-asserted-by":"publisher","first-page":"281","DOI":"10.1109\/HPCA.1996.501193","volume-title":"Second International Symposium on High-Performance Computer Architecture","author":"R. Espasa","year":"1996","unstructured":"Espasa, R., Valero, M.: Decoupled Vector Architectures. In: Second International Symposium on High-Performance Computer Architecture, pp. 281\u2013290. IEEE Computer Society Press, San Jose (1996)"},{"key":"41_CR3","volume-title":"Advanced Vector Architectures Parallel Architectures and Compilation Techniques (PACT 1997)","author":"L. Villa","year":"1997","unstructured":"Villa, L., Espasa, R., Valero, M.: Effective Usage of Vector Registers. In: Advanced Vector Architectures Parallel Architectures and Compilation Techniques (PACT 1997). IEEE Computer Society Press, San Francisco (1997)"},{"key":"41_CR4","doi-asserted-by":"crossref","unstructured":"Espasa, R., Valero, M.: Exploiting Instruction- and Data-Level Parallelism. IEEE Micro (September\/October 1997) (In conjunction with IEEE Computer Special Issue on Computing with a Billion Transistors)","DOI":"10.1109\/40.621210"},{"key":"41_CR5","volume-title":"A Victim Cache for Vector Registers International Conference on Supercomputing","author":"R. Espasa","year":"1997","unstructured":"Espasa, R., Valero, M.: A Victim Cache for Vector Registers International Conference on Supercomputing. ACM Computer Society Press, Vienna (1997)"},{"key":"41_CR6","doi-asserted-by":"crossref","unstructured":"Espasa, R., Valero, M.: Out-of-order Vector Architectures. In: 30th International Symposium on Microarchitecture (MICRO-30), North Carolina (1997)","DOI":"10.1109\/MICRO.1997.645807"},{"key":"41_CR7","doi-asserted-by":"crossref","unstructured":"Jouppi, N., Wall, D.: Available Instruction level parallelism for superscalar and superpipelined machines. ASPLOS, 272\u2013282 (1989)","DOI":"10.1145\/68182.68207"},{"key":"41_CR8","first-page":"243","volume-title":"22nd International Symposium on Computer Architecture","author":"M. Peiron","year":"1995","unstructured":"Peiron, M., Valero, M., Ayguade, E., Lang, T.: Vector Multiprocessors with Arbitrated Memory Access. In: 22nd International Symposium on Computer Architecture, pp. 243\u2013252. Santa Margherita Liguria, Italy (1995)"},{"issue":"2","key":"41_CR9","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1109\/40.491460","volume":"16","author":"K. Yeager","year":"1996","unstructured":"Yeager, K., et al.: The MIPS R10000 Superscalar Microprocessor. IEEE Micro\u00a016(2), 28\u201340 (1996)","journal-title":"IEEE Micro"},{"key":"41_CR10","unstructured":"Convex Assembly Language Reference Manual (C Series). Convex Press (1991)"},{"key":"41_CR11","unstructured":"Price, C.: MIPS IV Instruction Set, revision 3.1 MIPS Technologies, Inc., Mountain View, California (1995)"},{"key":"41_CR12","unstructured":"Espasa, R., Martorell, X.: Dixie: a trace generation system for the C3480. Technical Report CEPBA-TR-94-08, Universitat Politecnica de Catalunya (1994)"},{"key":"41_CR13","unstructured":"Burger, D., Austin, T., Bennett, S.: Evaluating Future Microprocessors: TheSimpleScalar ToolSet University of Wisconsin-Madison. Computer Sciences Department. Technical Report CS-TR-1308 (1996)"},{"key":"41_CR14","doi-asserted-by":"crossref","unstructured":"Quintana, F., Espasa, R., Valero, M.: A Case for Merging the ILP and DLP Paradigms. In: 6th Euromicro Workshop on Parallel and Distributed Processing, Madrid, Spain, pp. 217\u2013224 (1998)","DOI":"10.1109\/EMPDP.1998.647201"}],"container-title":["Lecture Notes in Computer Science","Vector and Parallel Processing \u2013 VECPAR\u201998"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/10703040_41","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,21]],"date-time":"2019-04-21T11:19:24Z","timestamp":1555845564000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/10703040_41"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999]]},"ISBN":["9783540662280","9783540485162"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/10703040_41","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1999]]}}}