{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T14:12:00Z","timestamp":1761401520408,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540258094"},{"type":"electronic","value":"9783540320173"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11422778_46","type":"book-chapter","created":{"date-parts":[[2010,7,13]],"date-time":"2010-07-13T20:01:28Z","timestamp":1279051288000},"page":"574-585","source":"Crossref","is-referenced-by-count":3,"title":["A Multizone Pipelined Cache for IP Routing"],"prefix":"10.1007","author":[{"given":"Soraya","family":"Kasnavi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Berube","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vincent C.","family":"Gaudet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 Nelson","family":"Amaral","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"46_CR1","doi-asserted-by":"crossref","unstructured":"Akhbarizadeh, M.J., Nourani, M.: Efficient prefix cache for network processors. In: 12th Annual IEEE Symposium on High Performance Interconnects, August 2004, pp. 41\u201346 (2004)","DOI":"10.1109\/CONECT.2004.1375199"},{"key":"46_CR2","doi-asserted-by":"crossref","unstructured":"Berube, P., Zinyk, A., Amaral, J.N., MacGregor, M.: The bank nth chance replacement policy for FPGA-based CAMs. In: 13th International Conference on Field Programmable Logic and Applications (FPL), Lisbon, Portugal (September 2003)","DOI":"10.1007\/978-3-540-45234-8_63"},{"key":"46_CR3","doi-asserted-by":"crossref","unstructured":"Chen, T., Baer, J.: Reducing memory latency via non-blocking and prefetching caches. In: 5th Int. Conf. Architectural Support for Programming Languages and Operating Systems, October 1992, pp. 51\u201361 (1992)","DOI":"10.1145\/143365.143486"},{"key":"46_CR4","unstructured":"Chiueh, T.-C., Pradhan, P.: Cache memory design for network processors. In: Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 2000, pp. 409\u2013419 (2000)"},{"key":"46_CR5","doi-asserted-by":"crossref","unstructured":"Chvets, I.L., MacGregor, M.: Multi-zone caches for accelerating IP routing table lookups. In: Merging Optical and IP Technologies Workshop on High Performance Switching and Routing, May 2002, pp. 121\u2013126 (2002)","DOI":"10.1109\/HPSR.2002.1024220"},{"key":"46_CR6","doi-asserted-by":"crossref","unstructured":"Chiueh, T.-C., Pradhan, P.: High performance IP routing table lookup using CPU caching. In: IEEE INFOCOM, vol.\u00a03, pp. 1421\u20131428 (1999)","DOI":"10.1109\/INFCOM.1999.752162"},{"key":"46_CR7","doi-asserted-by":"publisher","first-page":"325","DOI":"10.1109\/TVLSI.2004.824298","volume":"12","author":"A. Efthymiou","year":"2004","unstructured":"Efthymiou, A., Garside, J.D.: A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Transaction on Very Large Scale Integration (VLSI) Systems\u00a012, 325\u2013329 (2004)","journal-title":"IEEE Transaction on Very Large Scale Integration (VLSI) Systems"},{"key":"46_CR8","doi-asserted-by":"crossref","unstructured":"Farkas, K.I., Jouppi, N.P.: Complexity\/performance tradeoffs with non-blocking loads. In: 21st Int. Symposium on Computer Architecture, pp. 211\u2013222 (1994)","DOI":"10.1109\/ISCA.1994.288148"},{"key":"46_CR9","doi-asserted-by":"crossref","unstructured":"Feldmeier, D.C.: Improving gateway performance with a routing-table cache. In: IEEE INFOCOM 1988, March 1988, pp. 298\u2013307 (1988)","DOI":"10.1109\/INFCOM.1988.12930"},{"key":"46_CR10","unstructured":"Jen, C., Hsiao, H., Wang, D.: Power modeling and low-power design of content addressable memories. In: IEEE Int. Symposium on Circuits and Systems, May 2001, pp. 926\u2013929 (2001)"},{"key":"46_CR11","unstructured":"Kroft, D.: Lookup free instruction fetch\/prefetch cache organization. In: 8th Int. Symposium on Computer Architecture, May 1981, pp. 81\u201387 (1981)"},{"key":"46_CR12","doi-asserted-by":"crossref","unstructured":"Wang, H., Bhuyan, L.: Execution-driven simulation of IP router architectures. In: IEEE Int. Symposium on Network Computing and Applications, October 2001, pp. 145\u2013155 (2001)","DOI":"10.1109\/NCA.2001.962526"},{"key":"46_CR13","unstructured":"Liu, H.: Routing prefix caching in network processor design. In: Tenth International Conference on Computer Communications and Networks (October 2001)"},{"key":"46_CR14","doi-asserted-by":"crossref","unstructured":"Pagiamtzis, K., Sheikholeslami, A.: Pipelined match-lines and hierarchical search-lines for low-power content addressable memories. In: IEEE Custom Integrated Circuit Conference (September 2003)","DOI":"10.1109\/CICC.2003.1249423"},{"key":"46_CR15","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/65.912716","volume":"15","author":"M.A. Ruiz-Sanchez","year":"2001","unstructured":"Ruiz-Sanchez, M.A., Biersack, E.W., Dabbous, W.: Survey and taxonomy of IP address lookup algorithms. IEEE Network\u00a015, 8\u201323 (2001)","journal-title":"IEEE Network"},{"key":"46_CR16","doi-asserted-by":"crossref","unstructured":"Shyu, W.L., Wu, C.S., Hou, T.C.: Multilevel aligned IP prefix caching based on singleton information. In: GLOBECOM 2002, November 2002, vol.\u00a03, pp. 2345\u20132349 (2002)","DOI":"10.1109\/GLOCOM.2002.1189050"}],"container-title":["Lecture Notes in Computer Science","NETWORKING 2005. Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communications Systems"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11422778_46.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,22]],"date-time":"2025-02-22T21:55:52Z","timestamp":1740261352000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11422778_46"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540258094","9783540320173"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/11422778_46","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}