{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T17:59:06Z","timestamp":1725559146023},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540260325"},{"type":"electronic","value":"9783540321118"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11428831_75","type":"book-chapter","created":{"date-parts":[[2010,7,14]],"date-time":"2010-07-14T00:14:05Z","timestamp":1279066445000},"page":"607-614","source":"Crossref","is-referenced-by-count":2,"title":["Simulation of Parasitic Interconnect Capacitance for Present and Future ICs"],"prefix":"10.1007","author":[{"given":"Grzegorz","family":"Tosik","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zbigniew","family":"Lisik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malgorzata","family":"Langer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Janusz","family":"Wozny","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"75_CR1","unstructured":"The International Technology Roadmap for Semiconductors (2001), \n                    \n                      http:\/\/public.itrs.net"},{"issue":"6","key":"75_CR2","doi-asserted-by":"publisher","first-page":"530","DOI":"10.1109\/JSSC.1975.1050654","volume":"10","author":"A. Ruehli","year":"1975","unstructured":"Ruehli, A., Brennan, P.: Capacitance Models for Integrated Circuit Metalization Wires. Journal of Solid-State Integrated Circuits\u00a010(6), 530\u2013536 (1975)","journal-title":"Journal of Solid-State Integrated Circuits"},{"issue":"4","key":"75_CR3","doi-asserted-by":"publisher","first-page":"657","DOI":"10.1109\/4.663574","volume":"33","author":"M. Lee","year":"1998","unstructured":"Lee, M.: A Multilevel Parasitic Interconnect Capacitance Modeling and Extraction for Reliable VLSI On-Chip Clock Delay Evaluation. Journal of Solid-State Integrated Circuits\u00a033(4), 657\u2013661 (1998)","journal-title":"Journal of Solid-State Integrated Circuits"},{"issue":"2","key":"75_CR4","doi-asserted-by":"publisher","first-page":"295","DOI":"10.1109\/43.3160","volume":"7","author":"E. Barke","year":"1988","unstructured":"Barke, E.: Line-to-Ground Capacitance Calculation for VLSI: A Comparison. IEEE Transaction of Computer Added Design\u00a07(2), 295\u2013298 (1988)","journal-title":"IEEE Transaction of Computer Added Design"},{"key":"75_CR5","unstructured":"Chen, J.C., McGaughy, B., Sylvester, D., Hu, C.: An On-Chip Atto-Farad Interconnect Charge-Based Capacitance Measurement Technique. In: IEEE Tech. Dig. Int. Electron device Meeting (1996)"},{"key":"75_CR6","doi-asserted-by":"crossref","unstructured":"Jensen, O.P.: Calculating Wire Capacitance in Integrated Circuits. IEEE Circuits and Devices (3), 36\u201340 (1994)","DOI":"10.1109\/101.268864"},{"issue":"2","key":"75_CR7","doi-asserted-by":"publisher","first-page":"275","DOI":"10.1109\/JSSC.1982.1051729","volume":"17","author":"K.C. Saraswat","year":"1982","unstructured":"Saraswat, K.C., Mohammadi, F.: Effect of Scaling of Interconnections on the Time Delay of VLSi Circuits. Journal of Solid-State Circuits\u00a017(2), 275\u2013280 (1982)","journal-title":"Journal of Solid-State Circuits"},{"issue":"2","key":"75_CR8","doi-asserted-by":"publisher","first-page":"183","DOI":"10.1109\/T-ED.1983.21093","volume":"30","author":"T. Sakurai","year":"1983","unstructured":"Sakurai, T., Tamaru, K.: Simple Formulas for Two- and Three \u2013Dimensional Capacitances. IEEE Tran. On Electron Devices\u00a030(2), 183\u2013185 (1983)","journal-title":"IEEE Tran. On Electron Devices"},{"key":"75_CR9","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/55.144942","volume":"13","author":"J.H. Chern","year":"1992","unstructured":"Chern, J.H., Huang, J., Arledge, L., Li, P.C., Yang, P.: Multilevel metal capacitance models for CAD design synthesis systems. IEEE Electron Device Letters\u00a013, 32\u201334 (1992)","journal-title":"IEEE Electron Device Letters"},{"issue":"2","key":"75_CR10","doi-asserted-by":"publisher","first-page":"219","DOI":"10.1109\/66.843637","volume":"13","author":"S.-C. Wong","year":"2000","unstructured":"Wong, S.-C., Lee, T.G.Y., Ma, D.J., Chao, C.J.: An Empirical Three-Dimensional Crossover Capacitance Model for Multilevel Interconnect VLSI Circuits. IEEE Trans. Semiconductor Manufacxturing\u00a013(2), 219\u2013223 (2000)","journal-title":"IEEE Trans. Semiconductor Manufacxturing"},{"key":"75_CR11","unstructured":"Vector Fields, \n                    \n                      http:\/\/www.vectorfields.com\/op2d"},{"issue":"3","key":"75_CR12","doi-asserted-by":"publisher","first-page":"202","DOI":"10.1109\/TCAD.1983.1270037","volume":"2","author":"J. Rubinstein","year":"1983","unstructured":"Rubinstein, J., Penfield, P., Horowitz, M.A.: Signal Delay in RC Tree Networks. IEEE Transactions on Computer-Aided Design\u00a02(3), 202\u2013211 (1983)","journal-title":"IEEE Transactions on Computer-Aided Design"},{"issue":"11","key":"75_CR13","doi-asserted-by":"publisher","first-page":"2078","DOI":"10.1109\/16.877169","volume":"47","author":"J.A. Davis","year":"2000","unstructured":"Davis, J.A., Meindl, J.D.: Compact Distributed RLC Interconnect Models, Part II- Coupled line transient expressions and peak crosstalk in multilevel networks. IEEE Transactions on Electron Devices\u00a047(11), 2078\u20132087 (2000)","journal-title":"IEEE Transactions on Electron Devices"},{"issue":"1","key":"75_CR14","doi-asserted-by":"publisher","first-page":"83","DOI":"10.1109\/43.822622","volume":"19","author":"Y.I. Ismail","year":"2000","unstructured":"Ismail, Y.I., Friedman, E.G.: Equivalent Elmore Delay for RLC Trees. IEEE Transaction on Computer-Aided Design of Integrated Circuits and systems\u00a019(1), 83\u201396 (2000)","journal-title":"IEEE Transaction on Computer-Aided Design of Integrated Circuits and systems"},{"key":"75_CR15","doi-asserted-by":"publisher","first-page":"196","DOI":"10.1109\/EDL.1981.25399","volume":"EDL-2","author":"R.L. Dang","year":"1981","unstructured":"Dang, R.L., Shigyo, N.: A two-dimensional simulations of LSI interconnect capacitance. IEEE Electron Device Lett.\u00a0EDL-2, 196\u2013197 (1981)","journal-title":"IEEE Electron Device Lett."}],"container-title":["Lecture Notes in Computer Science","Computational Science \u2013 ICCS 2005"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11428831_75","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,16]],"date-time":"2019-03-16T14:19:09Z","timestamp":1552745949000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11428831_75"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540260325","9783540321118"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/11428831_75","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}