{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,13]],"date-time":"2025-10-13T19:50:39Z","timestamp":1760385039784},"publisher-location":"Berlin, Heidelberg","reference-count":5,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540265511"},{"type":"electronic","value":"9783540318934"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11504894_76","type":"book-chapter","created":{"date-parts":[[2010,4,9]],"date-time":"2010-04-09T08:17:40Z","timestamp":1270801060000},"page":"554-556","source":"Crossref","is-referenced-by-count":9,"title":["Hardware Architecture for Genetic Algorithms"],"prefix":"10.1007","author":[{"given":"Nadia","family":"Nedjah","sequence":"first","affiliation":[]},{"given":"Luiza","family":"de Macedo Mourelle","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"unstructured":"Bland, I.M., Megson, G.M.: Implementing a generic systolic array for genetic algorithms. In: Proc. 1st. On-Line Workshop on Soft Computing, pp. 268\u2013273 (1996)","key":"76_CR1"},{"unstructured":"Liu, J.: A general purpose hardware implementation of genetic algorithms, MSc. Thesis, University of North Carolina (1993)","key":"76_CR2"},{"key":"76_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"17","DOI":"10.1007\/3-540-44869-1_3","volume-title":"Artificial Neural Nets. Problem Solving Methods","author":"N. Nedjah","year":"2003","unstructured":"Nedjah, N., Mourelle, L.M.: Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron. In: Mira, J., \u00c1lvarez, J.R. (eds.) IWANN 2003. LNCS, vol.\u00a02687, pp. 17\u201324. Springer, Heidelberg (2003)"},{"doi-asserted-by":"crossref","unstructured":"Scott, S.D., Samal, A., Seth, S.: HGA: a hardware-based genetic algorithm. In: Proc. ACM\/SIGDA 3rd. International Symposium in Field-Programmable Gate Array, pp. 53\u201359 (1995)","key":"76_CR4","DOI":"10.1145\/201310.201319"},{"doi-asserted-by":"crossref","unstructured":"Turton, B.H., Arslan, T.: A parallel genetic VLSI architecture for combinatorial real-time applications \u2013 disc scheduling. In: Proc. IEE\/IEEE International Conference on Genetic Algorithms in Engineering Systems, pp. 88\u201393 (1994)","key":"76_CR5","DOI":"10.1049\/cp:19951097"}],"container-title":["Lecture Notes in Computer Science","Innovations in Applied Artificial Intelligence"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11504894_76","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T23:30:26Z","timestamp":1558999826000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11504894_76"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540265511","9783540318934"],"references-count":5,"URL":"https:\/\/doi.org\/10.1007\/11504894_76","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}