{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T01:56:18Z","timestamp":1783562178548,"version":"3.55.0"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540284741","type":"print"},{"value":"9783540319405","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11545262_32","type":"book-chapter","created":{"date-parts":[[2005,9,27]],"date-time":"2005-09-27T14:35:35Z","timestamp":1127831735000},"page":"441-455","source":"Crossref","is-referenced-by-count":344,"title":["A Very Compact S-Box for AES"],"prefix":"10.1007","author":[{"given":"D.","family":"Canright","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","reference":[{"key":"32_CR1","doi-asserted-by":"crossref","unstructured":"Canright, D.: A very compact Rijndael S-box. Technical Report NPS-MA-04-001, Naval Postgraduate School (September 2004)","DOI":"10.21236\/ADA434781"},{"key":"32_CR2","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"319","DOI":"10.1007\/978-3-540-45238-6_26","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2003","author":"P. Chodowiec","year":"2003","unstructured":"Chodowiec, P., Gaj, K.: Very compact FPGA implementation of the AES algorithm. In: Walter, C.D., Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 2003. LNCS, vol.\u00a02779, pp. 319\u2013333. Springer, Heidelberg (2003)"},{"key":"32_CR3","doi-asserted-by":"crossref","unstructured":"Jarvinen, K.U., Tommiska, M.T., Skytta, J.O.: A fully pipelined memoryless 17.8 gbps AES128 encryptor. In: FPGA 2003. ACM, New York (2003)","DOI":"10.1145\/611817.611848"},{"key":"32_CR4","volume-title":"Introduction to finite fields and their applications","author":"R. Lidl","year":"1986","unstructured":"Lidl, R., Niederreiter, H.: Introduction to finite fields and their applications. Cambridge, New York (1986)"},{"key":"32_CR5","volume-title":"The Theory of Error-Correcting Codes","author":"F.J. MacWilliams","year":"1977","unstructured":"MacWilliams, F.J., Sloane, N.J.A.: The Theory of Error-Correcting Codes. North-Holland, Amsterdam (1977)"},{"key":"32_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"323","DOI":"10.1007\/978-3-540-30574-3_22","volume-title":"Topics in Cryptology \u2013 CT-RSA 2005","author":"N. Mentens","year":"2005","unstructured":"Mentens, N., Batina, L., Preneel, B., Verbauwhede, I.: A systematic evaluation of compact hardware implementations for the Rijndael S-box. In: Menezes, A. (ed.) CT-RSA 2005. LNCS, vol.\u00a03376, pp. 323\u2013333. Springer, Heidelberg (2005)"},{"key":"32_CR7","doi-asserted-by":"crossref","unstructured":"Morioka, S., Satoh, A.: A 10 Gbps full-AES crypto design with a twisted-BDD S-box architecture. In: IEEE International Conference on Computer Design. IEEE, Los Alamitos (2002)","DOI":"10.1109\/ICCD.2002.1106754"},{"key":"32_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1007\/3-540-36400-5_14","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2002","author":"S. Morioka","year":"2003","unstructured":"Morioka, S., Satoh, A.: An optimized S-box circuit arthitecture for low power AES design. In: Kaliski Jr., B.S., Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 2002. LNCS, vol.\u00a02523, pp. 172\u2013186. Springer, Heidelberg (2003)"},{"key":"32_CR9","unstructured":"NIST. Recommendation for block cipher modes of operation. Technical Report SP 800-38A, National Institute of Standards and Technology (NIST) (December 2001)"},{"key":"32_CR10","unstructured":"NIST. Specification for the ADVANCED ENCRYPTION STANDARD (AES). Technical Report FIPS PUB 197, National Institute of Standards and Technology (NIST) (November 2001)"},{"key":"32_CR11","unstructured":"Paar, C.: Efficient VLSI Architectures for Bit-Parallel Computation in Galois Fields. PhD thesis, Institute for Experimental Mathematics. University of Essen, Germany (1994)"},{"key":"32_CR12","unstructured":"Rijmen, V.: Efficient implementation of the Rijndael S-box (2001), available at, http:\/\/www.esat.kuleuven.ac.be\/~rijmen\/rijndael\/sbox.pdf"},{"key":"32_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1007\/3-540-44709-1_16","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2001","author":"A. Rudra","year":"2001","unstructured":"Rudra, A., Dubey, P.K., Jutla, C.S., Kumar, V., Rao, J.R., Rohatgi, P.: Efficient Rijndael encryption implementation with composite field arithmetic. In: Ko\u00e7, \u00c7.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol.\u00a02162, pp. 171\u2013184. Springer, Heidelberg (2001)"},{"key":"32_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"239","DOI":"10.1007\/3-540-45682-1_15","volume-title":"Advances in Cryptology - ASIACRYPT 2001","author":"A. Satoh","year":"2001","unstructured":"Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A compact Rijndael hardware architecture with S-box optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol.\u00a02248, pp. 239\u2013254. Springer, Heidelberg (2001)"},{"key":"32_CR15","unstructured":"Satoh, A.: personal communication (July 2004)"},{"key":"32_CR16","unstructured":"Weaver, N., Wawrzynek, J.: High performance, compact AES implementations in Xilinx FPGAs (September 2002), available at, http:\/\/www.cs.berkeley.edu\/~nweaver\/papers\/AES_in_FPGAs.pdf"},{"key":"32_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1007\/3-540-45760-7_6","volume-title":"Topics in Cryptology - CT-RSA 2002","author":"J. Wolkerstorfer","year":"2002","unstructured":"Wolkerstorfer, J., Oswald, E., Lamberger, M.: An ASIC implementation of the AES Sboxes. In: Preneel, B. (ed.) CT-RSA 2002. LNCS, vol.\u00a02271, pp. 67\u201378. Springer, Heidelberg (2002)"}],"container-title":["Lecture Notes in Computer Science","Cryptographic Hardware and Embedded Systems \u2013 CHES 2005"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11545262_32.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T20:18:42Z","timestamp":1605644322000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11545262_32"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540284741","9783540319405"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/11545262_32","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2005]]}}}