{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,19]],"date-time":"2026-03-19T21:02:25Z","timestamp":1773954145962,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540290131","type":"print"},{"value":"9783540320807","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11556930_1","type":"book-chapter","created":{"date-parts":[[2010,9,28]],"date-time":"2010-09-28T21:18:41Z","timestamp":1285708721000},"page":"1-9","source":"Crossref","is-referenced-by-count":3,"title":["A Power-Efficient and Scalable Load-Store Queue Design"],"prefix":"10.1007","author":[{"given":"Fernando","family":"Castro","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Chaver","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis","family":"Pinuel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel","family":"Prieto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael C.","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Francisco","family":"Tirado","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"1_CR1","doi-asserted-by":"crossref","unstructured":"Kessler, R.E.: The Alpha 21264 Microprocessor. Technical Report, Compaq Computer Corporation (1999)","DOI":"10.1109\/40.755465"},{"key":"1_CR2","unstructured":"Calder, B., Reinman, G.: A Comparative Survey of Load Speculation Architectures. Journal of Instruction-Level Parallelism (May 2000)"},{"issue":"2","key":"1_CR3","doi-asserted-by":"publisher","first-page":"44","DOI":"10.1109\/MM.2003.1196114","volume":"23","author":"C. Nairy","year":"2003","unstructured":"Nairy, C., Soltis, D.: Itanium-2 Processor Microarchitecture. IEEE-Micro\u00a023(2), 44\u201355 (2003)","journal-title":"IEEE-Micro"},{"issue":"1","key":"1_CR4","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1147\/rd.461.0005","volume":"46","author":"J.M. Tendler","year":"2002","unstructured":"Tendler, J.M., Dodson, J.S., Fields Jr., J.S., Le, H., Sinharoy, B.: Power-4 System Microarchitecture. IBM Journal of Research and Development\u00a046(1), 5\u201326 (2002)","journal-title":"IBM Journal of Research and Development"},{"key":"1_CR5","doi-asserted-by":"crossref","unstructured":"Sethumadhavan, S., Desikan, R., Burger, D., Moore, C.R., Keckler, S.W.: Scalable Hardware Memory Disambiguation for High ILP Processors. In: Proceedings of MICRO-36 (December 2003)","DOI":"10.1109\/MICRO.2003.1253244"},{"key":"1_CR6","doi-asserted-by":"crossref","unstructured":"Austin, T., Larson, E., Ernst, D.: SimpleScalar: An Infrastructure for Computer System Modeling. Computer\u00a035(2) (February 2002)","DOI":"10.1109\/2.982917"},{"key":"1_CR7","doi-asserted-by":"crossref","unstructured":"Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In: 28-ISCA, G\u00f6teborg, Sweden (July 2001)","DOI":"10.1145\/342001.339657"},{"key":"1_CR8","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically charecterizing large scale program behavior. In: Proceedings of ASPLOS 2002 (October 2002)","DOI":"10.1145\/605402.605403"},{"issue":"6","key":"1_CR9","doi-asserted-by":"publisher","first-page":"118","DOI":"10.1109\/MM.2004.87","volume":"24","author":"S. Sethumadhavan","year":"2004","unstructured":"Sethumadhavan, S., Desikan, R., Burger, D., Moore, C.R., Keckler, S.W.: Scalable Hardware Memory Disambiguation for High ILP Processors. IEEE-Micro\u00a024(6), 118\u2013127 (2004)","journal-title":"IEEE-Micro"},{"key":"1_CR10","doi-asserted-by":"crossref","unstructured":"Park, I., Liang Ooi, C., Vijaykumar, T.N.: Reducing design complexity of the load-store queue. In: Proceedings of MICRO-36 (December 2003)","DOI":"10.1109\/MICRO.2003.1253245"},{"key":"1_CR11","doi-asserted-by":"crossref","unstructured":"Cain, H.W., Lipasti, M.H.: Memory Ordering: A Value-Based Approach. In: Proceedings of ISCA-31 (June 2004)","DOI":"10.1109\/ISCA.2004.1310766"},{"key":"1_CR12","unstructured":"Roth, A.: A high-bandwidth load-store unit for single- and multi- threaded processors. Technical Report, University of Pennsylvania (2004)"},{"key":"1_CR13","unstructured":"Baugh, L., Zilles, C.: Decomposing the Load-Store Queue by Function for Power Reduction and Scalability. In: Proceedings of PAC Conference (October 2004)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11556930_1.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T14:47:30Z","timestamp":1605624450000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11556930_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540290131","9783540320807"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/11556930_1","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2005]]}}}