{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:35:00Z","timestamp":1740548100979,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":24,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540290131"},{"type":"electronic","value":"9783540320807"}],"license":[{"start":{"date-parts":[[2005,1,1]],"date-time":"2005-01-01T00:00:00Z","timestamp":1104537600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11556930_28","type":"book-chapter","created":{"date-parts":[[2010,9,29]],"date-time":"2010-09-29T01:18:41Z","timestamp":1285723121000},"page":"267-276","source":"Crossref","is-referenced-by-count":1,"title":["Power Supply Selective Mapping for Accurate Timing Analysis"],"prefix":"10.1007","author":[{"given":"Mariagrazia","family":"Graziano","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cristiano","family":"Forzan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Pandini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"doi-asserted-by":"crossref","unstructured":"Chen, H.H., Ling, D.D.: Power Supply Noise Analysis Methodology for Deep- Submicron VLSI Chip Design. In: Proc. of Design Automation Conf., June 1997, pp. 638\u2013647 (1997)","key":"28_CR1","DOI":"10.1145\/266021.266307"},{"key":"28_CR2","doi-asserted-by":"publisher","first-page":"209","DOI":"10.1109\/96.704931","volume":"21","author":"H.H. Chen","year":"1998","unstructured":"Chen, H.H., Nealy, J.S.: Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis. IEEE Trans. on Components, Packaging, and Manufacturing Technology-Part B\u00a021, 209\u2013215 (1998)","journal-title":"IEEE Trans. on Components, Packaging, and Manufacturing Technology-Part B"},{"key":"28_CR3","doi-asserted-by":"publisher","first-page":"159","DOI":"10.1109\/43.980256","volume":"21","author":"M. Zhao","year":"2002","unstructured":"Zhao, M., Panda, R.V., Sapatnekar, S.S., Blaauw, D.: Hierarchical Analysis of Power Distribution Networks. IEEE Trans. on Computer-Aided Design\u00a021, 159\u2013168 (2002)","journal-title":"IEEE Trans. on Computer-Aided Design"},{"doi-asserted-by":"crossref","unstructured":"Nassif, S.R., Kozhaya, J.N.: Fast Power Grid Simulation. In: Proc. of Design Automation Conf., June 2000, pp. 156\u2013161 (2000)","key":"28_CR4","DOI":"10.1145\/337292.337359"},{"doi-asserted-by":"crossref","unstructured":"Kozhaya, J.N., Nassif, S.R., Najm, F.N.: Multigrid-like Technique for Power Analysis. In: Proc. of Intl. Conf. on Computer-Aided Design, November 2001, pp. 480\u2013487 (2001)","key":"28_CR5","DOI":"10.1109\/ICCAD.2001.968685"},{"doi-asserted-by":"crossref","unstructured":"Gowan, M.K., Biro, L.L., Jackson, D.B.: Power Considerations in the Design of the Alpha 21264 Microprocessor. In: Proc. of Design Automation Conf., June 1998, pp. 726\u2013731 (1998)","key":"28_CR6","DOI":"10.1145\/277044.277226"},{"doi-asserted-by":"crossref","unstructured":"Dharchoudhury, R., Panda, D.: Blaauw, and R. Vaidyanathan,Design and Analysis of Power Distribution Networks in PowerPC TM Microprocessors. In: Proc. of Design Automation Conf., June 1998, pp. 738\u2013743 (1998)","key":"28_CR7","DOI":"10.1145\/277044.277229"},{"key":"28_CR8","doi-asserted-by":"publisher","first-page":"849","DOI":"10.1109\/81.704824","volume":"45","author":"P. Larsson","year":"1998","unstructured":"Larsson, P.: Resonance and Damping in CMOS Circuits with On-Chip Decoupling Capacitance. IEEE Trans. on CAS-I\u00a045, 849\u2013858 (1998)","journal-title":"IEEE Trans. on CAS-I"},{"doi-asserted-by":"crossref","unstructured":"Bobba, S., Thorp, T., Aingaran, K., Liu, D.: IC Power Distribution Challenges. In: Proc. of Intl. Conf. on Computer-Aided Design, November 2001, pp. 643\u2013650 (2001)","key":"28_CR9","DOI":"10.1109\/ICCAD.2001.968729"},{"key":"28_CR10","doi-asserted-by":"publisher","first-page":"62","DOI":"10.1109\/6040.826763","volume":"23","author":"H.-R. Cha","year":"2000","unstructured":"Cha, H.-R., Kwon, O.-K.: An Analytical Model of Simultaneous Switching Noise in CMOS Systems. IEEE Trans. on Advanced Packaging\u00a023, 62\u201368 (2000)","journal-title":"IEEE Trans. on Advanced Packaging"},{"key":"28_CR11","doi-asserted-by":"publisher","first-page":"487","DOI":"10.1109\/TVLSI.2002.800533","volume":"10","author":"K.T. Tang","year":"2002","unstructured":"Tang, K.T., Friedman, E.G.: Simultaneous Switching Noise in On-Chip CMOS Power Distribution Networks. IEEE Trans. on VLSI Systems\u00a010, 487\u2013493 (2002)","journal-title":"IEEE Trans. on VLSI Systems"},{"doi-asserted-by":"crossref","unstructured":"Ajami, A.H., Banerjee, K., Mehrotra, A., Pedram, M.: Analysis of IR-Drop Scaling with Implications for Deep Submicron P\/G Network Design. In: Proc. of ISQED, March 2003, pp. 35\u201340 (2003)","key":"28_CR12","DOI":"10.1109\/ISQED.2003.1194706"},{"doi-asserted-by":"crossref","unstructured":"Jiang, Y.-M., Cheng, K.-T.: Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. In: Proc. of Design Automation Conf., June 1999, pp. 760\u2013765 (1999)","key":"28_CR13","DOI":"10.1145\/309847.310053"},{"key":"28_CR14","doi-asserted-by":"publisher","first-page":"635","DOI":"10.1109\/43.848085","volume":"19","author":"R. Saleh","year":"2000","unstructured":"Saleh, R., Hussain, S.Z., Rochel, S., Overhauser, D.: Clock Skew Verification in the Presence of IR-drop in the Power Distribution Network. IEEE Trans. on Computer-Aided Design\u00a019, 635\u2013744 (2000)","journal-title":"IEEE Trans. on Computer-Aided Design"},{"unstructured":"Liou, J.-J., Krstic, A., Jiang, Y.-M., Cheng, K.-T.: Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. In: Proc. of Intl. Conf. on Computer-Aided Design, November 2000, pp. 493\u2013496 (2000)","key":"28_CR15"},{"key":"28_CR16","doi-asserted-by":"publisher","first-page":"461","DOI":"10.1109\/TVLSI.2003.812310","volume":"11","author":"L.H. Chen","year":"2003","unstructured":"Chen, L.H., Marek-Sadowska, M., Brewer, F.: Buffer Delay Change in the Presence of Power and Ground Noise. IEEE Trans. of VLSI Systems\u00a011, 461\u2013473 (2003)","journal-title":"IEEE Trans. of VLSI Systems"},{"key":"28_CR17","first-page":"584","volume":"25","author":"T. Sakurai","year":"1990","unstructured":"Sakurai, T., Newton, A.R.: Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. IEEE Trans. on Computer-Aided Design\u00a025, 584\u2013594 (1990)","journal-title":"IEEE Trans. on Computer-Aided Design"},{"doi-asserted-by":"crossref","unstructured":"Ahmadi, R., Najm, F.N.: Timing Analysis in Presence of Power Supply and Ground Voltage Variations. In: Proc. of Intl. Conf. on Computer-Aided Design, November 2003, pp. 176\u2013183 (2003)","key":"28_CR18","DOI":"10.1109\/ICCAD.2003.159687"},{"doi-asserted-by":"crossref","unstructured":"Pant, S., Blaauw, D., Zolotov, V., Sundareswaran, S., Panda, R.: Vectorless Analysis of Supply Noise Induced Delay Variation. In: Proc. of Intl. Conf. on Computer-Aided Design, November 2003, pp. 184\u2013191 (2003)","key":"28_CR19","DOI":"10.1109\/ICCAD.2003.159688"},{"unstructured":"Standard Delay Format Specification, Open Verilog International, Version 3.0 (May 1995)","key":"28_CR20"},{"key":"28_CR21","doi-asserted-by":"publisher","first-page":"544","DOI":"10.1109\/43.506141","volume":"15","author":"F. Dartu","year":"1996","unstructured":"Dartu, F., Menezes, N., Pileggi, L.T.: Performance Computation of Precharacterized CMOS Gates with RC Loads. IEEE Trans. on Computer-Aided Design\u00a015, 544\u2013553 (1996)","journal-title":"IEEE Trans. on Computer-Aided Design"},{"doi-asserted-by":"crossref","unstructured":"Odabasiouglu, A., Celik, M., Pileggi, L.T.: PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm. In: Proc. Intl. Conf. on Computer-Aided Design, November 1997, pp. 58\u201365 (1997)","key":"28_CR22","DOI":"10.1109\/ICCAD.1997.643366"},{"unstructured":"ELDO TM User Guide, Mentor Graphics, Inc. (2001)","key":"28_CR23"},{"unstructured":"PrimeTime TM User Guide, Synopsys, Inc. (2003)","key":"28_CR24"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11556930_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T03:35:05Z","timestamp":1740540905000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11556930_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540290131","9783540320807"],"references-count":24,"URL":"https:\/\/doi.org\/10.1007\/11556930_28","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}