{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:34:36Z","timestamp":1740548076875,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":26,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540290131"},{"type":"electronic","value":"9783540320807"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11556930_45","type":"book-chapter","created":{"date-parts":[[2010,9,29]],"date-time":"2010-09-29T01:18:41Z","timestamp":1285723121000},"page":"436-445","source":"Crossref","is-referenced-by-count":0,"title":["Design of Variable Input Delay Gates for Low Dynamic Power Circuits"],"prefix":"10.1007","author":[{"given":"Tezaswi","family":"Raja","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vishwani D.","family":"Agrawal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Bushnell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"45_CR1","doi-asserted-by":"crossref","unstructured":"Agrawal, V.D.: Low Power Design by Hazard Filtering. In: Proc. of the International Conference on VLSI Design, pp. 193\u2013197 (1997)","DOI":"10.1109\/ICVD.1997.568075"},{"key":"45_CR2","doi-asserted-by":"crossref","unstructured":"Agrawal, V.D., Bushnell, M.L., Parthasarathy, G., Ramadoss, R.: Digital Circuit Design for Minimum Transient Energy and Linear Programming Method. In: Proc. of the International Conference on VLSI Design, pp. 434\u2013439 (1999)","DOI":"10.1109\/ICVD.1999.745194"},{"key":"45_CR3","unstructured":"Berkelaar, M., Jacobs, E.: Using Gate Sizing to Reduce Glitch Power. In: Proc. of the ProRISC Workshop on Circuits, Systems and Signal Processing, Mierlo, The Netherlands, pp. 183\u2013188 (1996)"},{"key":"45_CR4","first-page":"1424","volume":"15","author":"M. Berkelaar","year":"1996","unstructured":"Berkelaar, M., Buurman, P., Jess, J.: Computing Entire Area\/Power Consumption Versus Delay Trade-off Curve for Gate Sizing Using a Piecewise Linear Simulator. IEEE Transactions on Circuits and Systems\u00a015, 1424\u20131434 (1996)","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"45_CR5","doi-asserted-by":"crossref","unstructured":"Berkelaar, M., Jess, J.A.G.: Transistor Sizing in MOS Digital Circuits with Linear Programming. In: Proc. of the European Design Automation Conference, Mierlo, The Netherlands, pp. 217\u2013221 (1990)","DOI":"10.1109\/EDAC.1990.136648"},{"key":"45_CR6","doi-asserted-by":"crossref","unstructured":"Berkelaar, M., Jacobs, E.T.A.F.: Gate Sizing Using a Statistical Delay Model. In: Proc. of the Design Automation and Test in Europe Conference, Paris, France, pp. 283\u2013290 (2000)","DOI":"10.1145\/343647.343782"},{"key":"45_CR7","doi-asserted-by":"crossref","unstructured":"Sathyamurthy, H., Sapatnekar, S.S., Fishburn, J.P.: Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. In: Proc. of the International Conference on Computer-Aided Design, pp. 467\u2013470 (1995)","DOI":"10.1109\/ICCAD.1995.480158"},{"key":"45_CR8","doi-asserted-by":"crossref","unstructured":"Benini, L., DeMicheli, G., Macii, A., Macii, E., Poncino, M., Scarsi, R.: Glitch power minimization by gate freezing. In: Proc. of the Design Automation and Test in Europe Conference, p. 36 (1999)","DOI":"10.1145\/307418.307481"},{"key":"45_CR9","doi-asserted-by":"publisher","first-page":"151","DOI":"10.1049\/ip-cds:20010343","volume":"148","author":"S. Kim","year":"2001","unstructured":"Kim, S., Kim, J., Hwang, S.Y.: New Path Balancing Algorithm for Glitch Power Reduction. IEE Proceedings: Circuits, Devices and Systems\u00a0148, 151\u2013156 (2001)","journal-title":"IEE Proceedings: Circuits, Devices and Systems"},{"key":"45_CR10","doi-asserted-by":"crossref","unstructured":"Raja, T., Agrawal, V.D., Bushnell, M.L.: Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. In: Proc. of the International Conference on VLSI Design, pp. 527\u2013532 (2003)","DOI":"10.1109\/ICVD.2003.1183188"},{"key":"45_CR11","doi-asserted-by":"crossref","unstructured":"Raja, T., Agrawal, V.D., Bushnell, M.L.: CMOS Circuit design for Minimum Dynamic Power and Highest Speed. In: Proc. of the International Conference on VLSI Design, pp. 1035\u20131040 (2004)","DOI":"10.1109\/ICVD.2004.1261066"},{"key":"45_CR12","unstructured":"Raja, T., Agrawal, V.D., Bushnell, M.L.: Variable Input Delay Logic and Its Application to Low Power Design. In: Proc. of the International Conference on VLSI Design, pp. 598\u2013605 (2005)"},{"key":"45_CR13","unstructured":"Raja, T.: Minimum Dynamic Power Design with Variable Input Delay Logic. PhD thesis, Rutgers University, Dept. of ECE, Piscataway, New Jersey (2004)"},{"key":"45_CR14","doi-asserted-by":"crossref","unstructured":"Datta, S., Nag, S., Roy, K.: ASAP: A Transistor Sizing Tool for Area, Delay and Power Optimization of CMOS Circuits. In: Proc. of the IEEE International Symposium on Circuits and Systems, pp. 61\u201364 (1994)","DOI":"10.1109\/ISCAS.1994.408755"},{"key":"45_CR15","doi-asserted-by":"crossref","unstructured":"Musoll, E., Cortadella, J.: Optimizing cmos circuits for low power using transistor reordering. In: Proc. of the European Design Automation Conference, pp. 219\u2013223 (1995)","DOI":"10.1109\/EDTC.1996.494152"},{"key":"45_CR16","doi-asserted-by":"crossref","unstructured":"Hashimoto, M., Onodera, H., Tamaru, K.: A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. In: Proc. of the Design Automation Conference, pp. 446\u2013451 (1999)","DOI":"10.1145\/309847.309977"},{"key":"45_CR17","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-2325-3","volume-title":"Low Power Digital CMOS Design","author":"A.P. Chandrakasan","year":"1995","unstructured":"Chandrakasan, A.P., Brodersen, R.W.: Low Power Digital CMOS Design. Kluwer Academic Publishers, Boston (1995)"},{"key":"45_CR18","doi-asserted-by":"publisher","first-page":"473","DOI":"10.1109\/4.126534","volume":"27","author":"A.P. Chandrakasan","year":"1992","unstructured":"Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low Power CMOS Digital Design. IEEE Journal of Solid-State Circuits\u00a027, 473\u2013484 (1992)","journal-title":"IEEE Journal of Solid-State Circuits"},{"volume-title":"Low-Power CMOS Design","year":"1998","key":"45_CR19","unstructured":"Chandrakasan, A., Brodersen, R. (eds.): Low-Power CMOS Design. IEEE Press, New York (1998)"},{"key":"45_CR20","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5685-5","volume-title":"Low Power Design in Deep Submicron Electronics","author":"W. Nebel","year":"1997","unstructured":"Nebel, W., Mermet, J.: Low Power Design in Deep Submicron Electronics. Kluwer Academic Publishers, Boston (1997)"},{"volume-title":"Low Power Design Methodologies","year":"1996","key":"45_CR21","unstructured":"Rabaey, J.M., Pedram, M. (eds.): Low Power Design Methodologies. Kluwer Academic Publishers, Boston (1996)"},{"key":"45_CR22","volume-title":"Low Power Design Methodologies","author":"J.M. Rabaey","year":"1995","unstructured":"Rabaey, J.M., Pedram, M.: Low Power Design Methodologies. Kluwer Academic Publishers, Boston (1995)"},{"key":"45_CR23","volume-title":"Low-Power CMOS VLSI Circuit Design","author":"K. Roy","year":"2000","unstructured":"Roy, K., Prasad, S.C.: Low-Power CMOS VLSI Circuit Design. Wiley Interscience Publications, New York (2000)"},{"key":"45_CR24","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-6065-4","volume-title":"Practical Low Power Digital VLSI Design","author":"G. Yeap","year":"1998","unstructured":"Yeap, G.: Practical Low Power Digital VLSI Design. Kluwer Academic Publishers, Boston (1998)"},{"key":"45_CR25","volume-title":"Digital Integrated Circuits: A Design Perspective","author":"J. Rabaey","year":"2003","unstructured":"Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective. Prentice Hall, Upper Saddle River (2003)"},{"key":"45_CR26","volume-title":"Principles of CMOS VLSI Design: A Systems Approach","author":"N. Weste","year":"1985","unstructured":"Weste, N., Eshraghian, K.: Principles of CMOS VLSI Design: A Systems Approach. Addison Wesley Publications, Reading (1985)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11556930_45.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T03:35:05Z","timestamp":1740540905000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11556930_45"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540290131","9783540320807"],"references-count":26,"URL":"https:\/\/doi.org\/10.1007\/11556930_45","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}