{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:02:09Z","timestamp":1742382129939,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":6,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540290131"},{"type":"electronic","value":"9783540320807"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11556930_58","type":"book-chapter","created":{"date-parts":[[2010,9,29]],"date-time":"2010-09-29T01:18:41Z","timestamp":1285723121000},"page":"571-580","source":"Crossref","is-referenced-by-count":1,"title":["A Method to Design Compact Dual-rail Asynchronous Primitives"],"prefix":"10.1007","author":[{"given":"Alin","family":"Razafindraibe","sequence":"first","affiliation":[]},{"given":"Michel","family":"Robert","sequence":"additional","affiliation":[]},{"given":"Marc","family":"Renaudin","sequence":"additional","affiliation":[]},{"given":"Philippe","family":"Maurine","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"58_CR1","doi-asserted-by":"crossref","unstructured":"Chelcea, T., Bardsley, A., Edwards, D.A., Nowick\", S.M.: A Burst-Mode Oriented Back-End for the Balsa Synthesis System. In: Proceedings of DATE 2002, Paris, pp. 330\u2013337 (2002)","DOI":"10.1109\/DATE.2002.998294"},{"key":"58_CR2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-642-55989-1","volume-title":"Logic synthesis of asynchronous controllers and interfaces","author":"J. Cortadella","year":"2002","unstructured":"Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Logic synthesis of asynchronous controllers and interfaces. Springer, Heidelberg (2002) ISBN: 3-540-43152-7"},{"key":"58_CR3","unstructured":"Renaudin, M., et al.: TAST. In: Tutorial given at the 8th international Symposium on Advanced Research in Asynchronous Circuits and Systems, Manchester, UK, April 8-11 (2002)"},{"key":"58_CR4","unstructured":"Piguet, C., Zhand, J.: Electrical Design of Dynamic and Static Speed Independent CMOS Circuits from Signal Transistion Graphs. In: PATMOS 1998, pp. 357\u2013366 (1998)"},{"key":"58_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"181","DOI":"10.1007\/978-3-540-39762-5_20","volume-title":"Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation","author":"P. Maurine","year":"2003","unstructured":"Maurine, P., Rigaud, J.B., Bouesse, F., Sicard, G., Renaudin, M.: Static Implementation of QDI asynchronousprimitives. In: Chico, J.J., Macii, E. (eds.) PATMOS 2003. LNCS, vol.\u00a02799, pp. 181\u2013191. Springer, Heidelberg (2003)"},{"key":"58_CR6","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-3385-3","volume-title":"Principles of Asynchronous Circuit Design - A Systems Perspective","author":"J. Sparso","year":"2001","unstructured":"Sparso, J., Furber, S.: Principles of Asynchronous Circuit Design - A Systems Perspective. Kluwer Academic Publishers, Dordrecht (2001)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11556930_58.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T03:34:39Z","timestamp":1740540879000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11556930_58"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540290131","9783540320807"],"references-count":6,"URL":"https:\/\/doi.org\/10.1007\/11556930_58","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}