{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:34:59Z","timestamp":1740548099927,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540290131"},{"type":"electronic","value":"9783540320807"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11556930_62","type":"book-chapter","created":{"date-parts":[[2010,9,29]],"date-time":"2010-09-29T01:18:41Z","timestamp":1285723121000},"page":"609-617","source":"Crossref","is-referenced-by-count":0,"title":["Fast Low-Power 64-Bit Modular Hybrid Adder"],"prefix":"10.1007","author":[{"given":"Stefania","family":"Perri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pasquale","family":"Corsonello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giuseppe","family":"Cocorullo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"62_CR1","doi-asserted-by":"crossref","unstructured":"Kogge, P.M., Stone, H.S.: A parallel algorithm for efficient solution of a general class of recurrence equations. IEEE Trans. on Computers\u00a0C22(8) (1973)","DOI":"10.1109\/TC.1973.5009159"},{"key":"62_CR2","doi-asserted-by":"crossref","unstructured":"Brent, R.P., Kung, H.T.: A regular layout for parallel adders. IEEE Trans. on Computers\u00a0C31(2) (1982)","DOI":"10.1109\/TC.1982.1675982"},{"key":"62_CR3","doi-asserted-by":"crossref","unstructured":"Lynch, T., Swartzlander, E.E.: A spanning-tree carry-look-ahead adder. IEEE Trans. on Comp.\u00a041(8) (1992)","DOI":"10.1109\/12.156535"},{"key":"62_CR4","doi-asserted-by":"crossref","unstructured":"Kantabutra, V.: A recursive carry-look-ahead\/carry-select hybrid adder. IEEE Trans. on Comp.\u00a042(12) (1993)","DOI":"10.1109\/12.260639"},{"key":"62_CR5","unstructured":"Woo, R., Lee, S., Yoo, H.: A 670ps, 64-bit dynamic low-power adder design. In: Proc. of IEEE ISCAS Conference, Geneva, May 2000, pp. 28\u201331 (2000)"},{"key":"62_CR6","doi-asserted-by":"crossref","unstructured":"Perri, S., Corsonello, P., Staino, G.: A low-power sub-nanosecond standard-cells based adder. In: Proceedings of the IEEE ICECS Conference, Sharjah, Arab Emirates, December 2003, pp. 296\u2013299 (2003)","DOI":"10.1109\/ICECS.2003.1302035"},{"issue":"10","key":"62_CR7","doi-asserted-by":"publisher","first-page":"1163","DOI":"10.1109\/12.257703","volume":"42","author":"A. Tyagi","year":"1993","unstructured":"Tyagi, A.: A reduced-area scheme for carry-select adders. IEEE Trans. on Comp.\u00a042(10), 1163\u20131170 (1993)","journal-title":"IEEE Trans. on Comp."},{"issue":"6","key":"62_CR8","doi-asserted-by":"publisher","first-page":"497","DOI":"10.1049\/ip-cds:20040807","volume":"151","author":"S. Perri","year":"2004","unstructured":"Perri, S., Corsonello, P., Pezzimenti, F., Kantabutra, V.: Fast and Energy-Efficient Manchester Carry-ByPass Adders. IEE Proceedings on Circuits, Devices and Systems\u00a0151(6), 497\u2013502 (2004)","journal-title":"IEE Proceedings on Circuits, Devices and Systems"},{"key":"62_CR9","unstructured":"Kim, J.J., Joshi, R., Chuang, C.T., Roy, K.: SOI-Optimized 64-bit High-Speed CMOS Adder Design. In: Proceedings of Symposium on VLSI Circuits Digest of Technical Papers, June 2002, pp. 122\u2013125 (2002)"},{"key":"62_CR10","doi-asserted-by":"crossref","unstructured":"Dao, H., Oklobdzija, V.G.: Application of Logical Effort Technique for Speed Optimization and Analysis of Representative Adders. In: Proceedings of the 35th Annual Asilomar Conference on Signals, Systems and Computers, California (USA), November 2001, vol.\u00a02, pp. 1666\u20131669 (2001)","DOI":"10.1109\/ACSSC.2001.987768"},{"issue":"3","key":"62_CR11","doi-asserted-by":"publisher","first-page":"235","DOI":"10.1109\/TVLSI.2004.824305","volume":"12","author":"A. Neve","year":"2004","unstructured":"Neve, A., Schettler, H., Ludwig, T., Flandre, D.: Power-Delay Product Minimizations in High-Performance 64-bit Carry-Select Adders. IEEE Trans. On VLSI Systems\u00a012(3), 235\u2013244 (2004)","journal-title":"IEEE Trans. On VLSI Systems"},{"key":"62_CR12","doi-asserted-by":"crossref","unstructured":"Simonen, P., Heinonen, A., Kuulusa, M., Nurmi, J.: Comparison of bulk and SOI CMOS technologies in a DSP Processor Circuit Implementation. In: Proceedings of the 13th International Conference on Microelectronics, Rabat, Marocco (October 2001)","DOI":"10.1109\/ICM.2001.997499"},{"key":"62_CR13","volume-title":"Digital Integrated Circuits - A Design Perspective","author":"J.M. Rabaey","year":"2003","unstructured":"Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits - A Design Perspective, 2nd edn. Prentice Hall, New Jersey (2003)","edition":"2"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11556930_62.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T03:34:49Z","timestamp":1740540889000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11556930_62"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540290131","9783540320807"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/11556930_62","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}