{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:36:59Z","timestamp":1725550619240},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540291053"},{"type":"electronic","value":"9783540320302"}],"license":[{"start":{"date-parts":[[2005,1,1]],"date-time":"2005-01-01T00:00:00Z","timestamp":1104537600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11560548_23","type":"book-chapter","created":{"date-parts":[[2005,10,6]],"date-time":"2005-10-06T05:38:22Z","timestamp":1128577102000},"page":"301-316","source":"Crossref","is-referenced-by-count":19,"title":["On the Verification of Memory Management Mechanisms"],"prefix":"10.1007","author":[{"given":"Iakov","family":"Dalinger","sequence":"first","affiliation":[]},{"given":"Mark","family":"Hillebrand","sequence":"additional","affiliation":[]},{"given":"Wolfgang","family":"Paul","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"23_CR1","unstructured":"Boyer, R.S., et al.: Special issue on system verification. (JAR)\u00a05 (1989)"},{"key":"23_CR2","volume-title":"A Computational Logic Handbook","author":"R.S. Boyer","year":"1988","unstructured":"Boyer, R.S., Moore, J.S.: A Computational Logic Handbook. Academic Press, London (1988)"},{"key":"23_CR3","doi-asserted-by":"crossref","unstructured":"Hunt, W.A.: Microprocessor design verification. In: JAR [1], pp. 429\u2013460","DOI":"10.1007\/BF00243132"},{"key":"23_CR4","unstructured":"Moore, J.S.: A mechanically verified language implementation. In: JAR [1], pp. 461\u2013492"},{"key":"23_CR5","unstructured":"Young, W.D.: A mechanically verified code generator. In: JAR [1], pp. 493\u2013518"},{"key":"23_CR6","unstructured":"Bevier, W.R.: Kit and the short stack. In: JAR [1], pp. 519\u2013530"},{"key":"23_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"161","DOI":"10.1007\/978-3-540-40007-3_11","volume-title":"Formal Methods at the Crossroads. From Panacea to Foundational Support","author":"J.S. Moore","year":"2003","unstructured":"Moore, J.S.: A grand challenge proposal for formal methods: A verified stack. In: Aichernig, B.K., Maibaum, T. (eds.) Formal Methods at the Crossroads. From Panacea to Foundational Support. LNCS, vol.\u00a02757, pp. 161\u2013172. Springer, Heidelberg (2003)"},{"key":"23_CR8","unstructured":"The Verisoft Consortium: The Verisoft Project (2003), http:\/\/www.verisoft.de\/"},{"key":"23_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1007\/11541868_1","volume-title":"Theorem Proving in Higher Order Logics","author":"M. Gargano","year":"2005","unstructured":"Gargano, M., Hillebrand, M., Leinenbach, D., Paul, W.: On the correctness of operating system kernels. In: Hurd, J., Melham, T. (eds.) TPHOLs 2005. LNCS, vol.\u00a03603, pp. 1\u201316. Springer, Heidelberg (2005)"},{"key":"23_CR10","volume-title":"SEFM\u00a0 2005","author":"D. Leinenbach","year":"2005","unstructured":"Leinenbach, D., Paul, W., Petrova, E.: Towards the formal verification of a C0 compiler: Code generation and implementation correctness. In: Aichernig, B., Beckert, B. (eds.) SEFM\u00a0 2005. IEEE Computer Society, Los Alamitos (2005)"},{"key":"23_CR11","volume-title":"ICCD 2005","author":"M. Hillebrand","year":"2005","unstructured":"Hillebrand, M., In der Rieden, T., Paul, W.: Dealing with I\/O devices in the context of pervasive system verification. In: ICCD 2005. IEEE Computer Society, Los Alamitos (2005) (to appear)"},{"key":"23_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1007\/978-3-540-39724-3_7","volume-title":"Correct Hardware Design and Verification Methods","author":"S. Beyer","year":"2003","unstructured":"Beyer, S., Jacobi, C., Kr\u00f6ning, D., Leinenbach, D., Paul, W.: Instantiating uninterpreted functional units and memory system: Functional verification of the VAMP. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol.\u00a02860, pp. 51\u201365. Springer, Heidelberg (2003)"},{"key":"23_CR13","unstructured":"Beyer, S.: Putting It All Together: Formal Verification of the VAMP. PhD thesis, Saarland University, Saarbr\u00fccken, Germany (2005)"},{"key":"23_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"135","DOI":"10.1007\/BFb0028740","volume-title":"Computer Aided Verification","author":"J. Sawada","year":"1998","unstructured":"Sawada, J., Hunt, W.A.: Processor verification with precise exceptions and speculative execution. In: Y. Vardi, M. (ed.) CAV 1998. LNCS, vol.\u00a01427, pp. 135\u2013146. Springer, Heidelberg (1998)"},{"key":"23_CR15","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-662-04267-0","volume-title":"Computer Architecture: Complexity and Correctness","author":"S.M. M\u00fcller","year":"2000","unstructured":"M\u00fcller, S.M., Paul, W.J.: Computer Architecture: Complexity and Correctness. Springer, Heidelberg (2000)"},{"key":"23_CR16","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"748","DOI":"10.1007\/3-540-55602-8_217","volume-title":"Automated Deduction - CADE-11","author":"S. Owre","year":"1992","unstructured":"Owre, S., Shankar, N., Rushby, J.M.: PVS: A prototype verification system. In: Kapur, D. (ed.) CADE 1992. LNCS, vol.\u00a0607, pp. 748\u2013752. Springer, Heidelberg (1992)"},{"key":"23_CR17","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"98","DOI":"10.1007\/978-3-540-30494-4_8","volume-title":"Formal Methods in Computer-Aided Design","author":"M. Aagaard","year":"2004","unstructured":"Aagaard, M., Ciubotariu, V., Higgins, J., Khalvati, F.: Combining equivalence verification and completion functions. In: Hu, A.J., Martin, A.K. (eds.) FMCAD 2004. LNCS, vol.\u00a03312, pp. 98\u2013112. Springer, Heidelberg (2004)"},{"key":"23_CR18","unstructured":"Paul, W., Dimova, D., Mancino, M.: Skript zur Vorlesung Systemarchitektur (2004), http:\/\/www-wjp.cs.uni-sb.de\/publikationen\/Skript.pdf"},{"key":"23_CR19","unstructured":"Hillebrand, M.: Address Spaces and Virtual Memory: Specification, Implementation, and Correctnesss. PhD thesis, Saarland University, Saarbr\u00fccken, Germany (2005)"},{"key":"23_CR20","unstructured":"Kr\u00f6ning, D.: Formal Verification of Pipelined Microprocessors. PhD thesis, Saarland University, Saarbr\u00fccken, Germany (2001)"}],"container-title":["Lecture Notes in Computer Science","Correct Hardware Design and Verification Methods"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11560548_23","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,10]],"date-time":"2020-04-10T00:43:15Z","timestamp":1586479395000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11560548_23"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540291053","9783540320302"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/11560548_23","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}