{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,3]],"date-time":"2025-09-03T10:17:19Z","timestamp":1756894639030},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540291053"},{"type":"electronic","value":"9783540320302"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11560548_4","type":"book-chapter","created":{"date-parts":[[2005,10,6]],"date-time":"2005-10-06T09:38:22Z","timestamp":1128591502000},"page":"5-19","source":"Crossref","is-referenced-by-count":16,"title":["Wired: Wire-Aware Circuit Design"],"prefix":"10.1007","author":[{"given":"Emil","family":"Axelsson","sequence":"first","affiliation":[]},{"given":"Koen","family":"Claessen","sequence":"additional","affiliation":[]},{"given":"Mary","family":"Sheeran","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"4_CR1","doi-asserted-by":"publisher","first-page":"649","DOI":"10.1145\/37888.37992","volume-title":"DAC 1987: Proceedings of the 24th ACM\/IEEE conference on Design automation","author":"B. Becker","year":"1987","unstructured":"Becker, B., Hotz, G., Kolla, R., Molitor, P., Osthof, H.-G.: Hierarchical design based on a calculus of nets. In: DAC 1987: Proceedings of the 24th ACM\/IEEE conference on Design automation, pp. 649\u2013653. ACM Press, New York (1987)"},{"key":"4_CR2","doi-asserted-by":"crossref","unstructured":"Brent, R.P., Kung, H.T.: A regular layout for parallel adders. IEEE Transactions on Computers\u00a0C-31 (1982)","DOI":"10.1109\/TC.1982.1675982"},{"key":"4_CR3","doi-asserted-by":"crossref","unstructured":"Brock, B., Hunt Jr., W.A.: The DUAL-EVAL Hardware Description Language and Its Use in the Formal Specification and Verification of the FM9001 Microprocessor. Formal Methods in System Design\u00a011(1) (1997)","DOI":"10.1023\/A:1008685826293"},{"key":"4_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"355","DOI":"10.1007\/3-540-44798-9_28","volume-title":"Correct Hardware Design and Verification Methods","author":"K. Claessen","year":"2001","unstructured":"Claessen, K., Sheeran, M., Singh, S.: The Design and Verification of a Sorter Core. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol.\u00a02144, p. 355. Springer, Heidelberg (2001)"},{"key":"4_CR5","volume-title":"Proc. 34th Asilomar Conf.","author":"Z. Huang","year":"2000","unstructured":"Huang, Z., Ercegovac, M.: Effect of Wire Delay on the Design of Prefix Adders in Deep-Submicron Technology. In: Proc. 34th Asilomar Conf. IEEE, Los Alamitos (2000)"},{"key":"4_CR6","volume-title":"Formal Methods for VLSI Design","author":"G. Jones","year":"1990","unstructured":"Jones, G., Sheeran, M.: Circuit design in Ruby. In: Staunstrup, J. (ed.) Formal Methods for VLSI Design. North-Holland, Amsterdam (1990)"},{"key":"4_CR7","volume-title":"Digital Integrated Circuits","author":"J.M. Rabaey","year":"2003","unstructured":"Rabaey, J.M., et al.: Digital Integrated Circuits. Prentice Hall, Englewood Cliffs (2003)"},{"key":"4_CR8","doi-asserted-by":"crossref","unstructured":"Sheeran, M.: \u03bcFP, an algebraic VLSI design language, D.Phil. Thesis. Oxford University (1983)","DOI":"10.1145\/800055.802026"},{"key":"4_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1007\/978-3-540-30494-4_2","volume-title":"Formal Methods in Computer-Aided Design","author":"M. Sheeran","year":"2004","unstructured":"Sheeran, M.: Generating fast multipliers using clever circuits. In: Hu, A.J., Martin, A.K. (eds.) FMCAD 2004. LNCS, vol.\u00a03312, pp. 6\u201320. Springer, Heidelberg (2004)"},{"key":"4_CR10","unstructured":"SIA: National Technology Roadmap for Semiconductors (1997)"},{"key":"4_CR11","doi-asserted-by":"crossref","unstructured":"Sklansky, J.: Conditional-sum addition logic. IRE Trans. Electron. Comput.\u00a0EC-9 (1960)","DOI":"10.1109\/TEC.1960.5219822"},{"key":"4_CR12","volume-title":"Design and Test in Europe (DATE)","author":"G. Spirakis","year":"2004","unstructured":"Spirakis, G.: Opportunities and challenges in building silicon products at 65nm and beyond. In: Design and Test in Europe (DATE). IEEE, Los Alamitos (2004)"}],"container-title":["Lecture Notes in Computer Science","Correct Hardware Design and Verification Methods"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11560548_4.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T19:50:29Z","timestamp":1605642629000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11560548_4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540291053","9783540320302"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/11560548_4","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}