{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:38:21Z","timestamp":1725550701594},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540296430"},{"type":"electronic","value":"9783540321088"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11572961_17","type":"book-chapter","created":{"date-parts":[[2005,10,18]],"date-time":"2005-10-18T11:06:07Z","timestamp":1129633567000},"page":"200-214","source":"Crossref","is-referenced-by-count":6,"title":["Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures"],"prefix":"10.1007","author":[{"given":"Jie S.","family":"Hu","sequence":"first","affiliation":[]},{"given":"G. M.","family":"Link","sequence":"additional","affiliation":[]},{"given":"Johnsy K.","family":"John","sequence":"additional","affiliation":[]},{"given":"Shuai","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Sotirios G.","family":"Ziavras","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"17_CR1","unstructured":"Hp nonstop himalaya, http:\/\/nonstop.compaq.com\/"},{"key":"17_CR2","doi-asserted-by":"crossref","unstructured":"Austin, T.: Diva: A reliable substrate for deep submicron microarchitecture design. In: Proc. the 32nd Annual IEEE\/ACM International Symposium on Microarchitecture, November 1999, pp. 196\u2013207 (1999)","DOI":"10.1109\/MICRO.1999.809458"},{"key":"17_CR3","doi-asserted-by":"crossref","unstructured":"Burger, D., Austin, T.M.: The simplescalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin (1997)","DOI":"10.1145\/268806.268810"},{"key":"17_CR4","doi-asserted-by":"crossref","unstructured":"Gomaa, M., Scarbrough, C., Vijaykumar, T., Pomeranz, I.: Transient-fault recovery for chip multiprocessors. In: Proc. the International Symposium on Computer Architecture, June 2003, pp. 98\u2013109 (2003)","DOI":"10.1145\/859618.859631"},{"key":"17_CR5","unstructured":"Hinton, G., Sager, D., Upton, M., Boggs, D.,, D.C.: The microarchitecture of the pentium 4 processor. Intel Technical Journal Q1 2001 Issue (February 2001)"},{"key":"17_CR6","doi-asserted-by":"crossref","unstructured":"Mendelson, A., Suri, N.: Designing high-performance and reliable superscalar architectures: The out of order reliable superscalar (o3rs) approach. In: Proc. of the International Conference on Dependable Systems and Networks (June 2000)","DOI":"10.1109\/ICDSN.2000.857578"},{"key":"17_CR7","doi-asserted-by":"crossref","unstructured":"Mukherjee, S.S., Kontz, M., Reinhardt, S.K.: Detailed design and evaluation of redundant multithreading alternatives. In: Proc. the 29th Annual International Symposium on Computer Architecture, May 2002, pp. 99\u2013110 (2002)","DOI":"10.1109\/ISCA.2002.1003566"},{"key":"17_CR8","unstructured":"Namjoo, M., McCluskey, E.: Watchdog processors and detection of malfunctions at the system level. Technical Report 81-17, CRC (December 1981)"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Parashar, A., Gurumurthi, S., Sivasubramaniam, A.: A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy. In: Proc. the 31st Annual International Symposium on Computer Architecture (June 2004)","DOI":"10.1109\/ISCA.2004.1310789"},{"key":"17_CR10","doi-asserted-by":"crossref","unstructured":"Ray, J., Hoe, J., Falsafi, B.: Dual use of superscalar datapath for transient-fault detection and recovery. In: Proc. the 34th Annual IEEE\/ACM International Symposium on Microarchitecture, December 2001, pp. 214\u2013224 (2001)","DOI":"10.1109\/MICRO.2001.991120"},{"key":"17_CR11","doi-asserted-by":"crossref","unstructured":"Reinhardt, S., Mukherjee, S.: Transient fault detection via simultaneous multithreading. In: Proc. the 27th Annual International Symposium on Computer Architecture, June 2000, pp. 25\u201336 (2000)","DOI":"10.1145\/339647.339652"},{"key":"17_CR12","doi-asserted-by":"crossref","unstructured":"Rotenberg, E.: Ar-smt: A microarchitectural approach to fault tolerance in microprocessors. In: Proc. the International Symposium on Fault-Tolerant Computing, June 1999, pp. 84\u201391 (1999)","DOI":"10.1109\/FTCS.1999.781037"},{"key":"17_CR13","doi-asserted-by":"crossref","unstructured":"Sastry, S.S., Palacharla, S., Smith, J.E.: Exploiting idle floating point resources for integer execution. In: Proc. ACM SIGPLAN 1998 Conf. Programming Language Design and Implementation, June 1998, pp. 118\u2013129 (1998)","DOI":"10.1145\/277650.277709"},{"key":"17_CR14","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically characterizing large scale program behavior. In: The 10th International Conference on Architectural Support for Programming Languages and Operating Systems (October 2002)","DOI":"10.1145\/605397.605403"},{"key":"17_CR15","doi-asserted-by":"crossref","unstructured":"Shivakumar, P., et al.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proc. International Conference on Dependable Systems and Networks, June 2002, pp. 389\u2013398 (2002)","DOI":"10.1109\/DSN.2002.1028924"},{"issue":"2","key":"17_CR16","doi-asserted-by":"publisher","first-page":"12","DOI":"10.1109\/40.755464","volume":"19","author":"T.J. Slegel","year":"1999","unstructured":"Slegel, T.J., et al.: IBM\u2019s S\/390 G5 microprocessor design. IEEE Micro\u00a019(2), 12\u201323 (1999)","journal-title":"IEEE Micro"},{"key":"17_CR17","doi-asserted-by":"crossref","unstructured":"Smolens, J., Kim, J., Hoe, J.C., Falsafi, B.: Efficient resource sharing in concurrent error detecting superscalar microarchitecture. In: ACM\/IEEE International Symposium on Microarchitecture (MICRO) (December 2004)","DOI":"10.1109\/MICRO.2004.19"},{"key":"17_CR18","doi-asserted-by":"crossref","unstructured":"Sundaramoorthy, K., Purser, Z., Rotenburg, E.: Slipstream processors: Improving both performance and fault tolerance. In: Proc. the 9th International Conference on Architectural Support for Programming Languages and Operating systems, pp. 257\u2013268 (2000)","DOI":"10.1145\/378993.379247"},{"key":"17_CR19","doi-asserted-by":"crossref","unstructured":"Vijaykumar, T., Pomeranz, I., Cheng, K.: Transient-fault recovery via simultaneous multithreading. In: Proc. the 29th Annual International Symposium on Computer Architecture, May 2002, pp. 87\u201398 (2002)","DOI":"10.1109\/ISCA.2002.1003565"},{"issue":"1","key":"17_CR20","doi-asserted-by":"publisher","first-page":"3","DOI":"10.1147\/rd.401.0003","volume":"40","author":"J.F. Ziegler","year":"1996","unstructured":"Ziegler, J.F., et al.: IBM experiments in soft fails in computer electronics (1978 - 1994). IBM Journal of Research and Development\u00a040(1), 3\u201318 (1996)","journal-title":"IBM Journal of Research and Development"}],"container-title":["Lecture Notes in Computer Science","Advances in Computer Systems Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11572961_17.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T19:55:40Z","timestamp":1605642940000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11572961_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540296430","9783540321088"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/11572961_17","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}