{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:38:42Z","timestamp":1725550722620},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540296430"},{"type":"electronic","value":"9783540321088"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11572961_61","type":"book-chapter","created":{"date-parts":[[2005,10,18]],"date-time":"2005-10-18T11:06:07Z","timestamp":1129633567000},"page":"750-760","source":"Crossref","is-referenced-by-count":3,"title":["A Memory Bandwidth Effective Cache Store Miss Policy"],"prefix":"10.1007","author":[{"given":"Hou","family":"Rui","sequence":"first","affiliation":[]},{"given":"Fuxin","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Weiwu","family":"Hu","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"61_CR1","doi-asserted-by":"crossref","unstructured":"Tullsen, D.M., Eggers, S.J., Levy, H.M., et al.: Simultaneous Multithreading: Maximizing On-Chip Parallelism. In: 22nd Annual International Symposium on Computer Architecture (1995)","DOI":"10.1145\/223982.224449"},{"key":"61_CR2","unstructured":"Hu, W., Tang, Z.: Microarchitecture design of the Godson-1 processor. Chinese Journal of Computers, 385\u2013396 (April 2003) (in Chinese)"},{"key":"61_CR3","doi-asserted-by":"crossref","unstructured":"Hu, W.-W., Zhang, F.-X., Li, Z.-S.: Microarchitecture of the Godson-2 Processor. Journal of Computer Science and Technology\u00a020(2) (March 2005)","DOI":"10.1007\/s11390-005-0243-6"},{"key":"61_CR4","volume-title":"Computer Architecture: A Quantitative Approach","author":"D. Patterson","year":"1996","unstructured":"Patterson, D., Hennessy, J.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Inc., San Francisco (1996)"},{"key":"61_CR5","unstructured":"McCalpin, J.D.: STREAM: Sustainable Memory Bandwidth in High Performance Computers, http:\/\/www.cs.virginia.edu\/stream\/"},{"key":"61_CR6","doi-asserted-by":"publisher","first-page":"28","DOI":"10.1109\/40.491460","volume":"16","author":"K. Yeager","year":"1996","unstructured":"Yeager, K.: The MIPS R10000 superscalar microprocessor. IEEE Micro\u00a016, 28\u201341 (1996)","journal-title":"IEEE Micro"},{"key":"61_CR7","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/40.755465","volume":"19","author":"R. Kessler","year":"1999","unstructured":"Kessler, R.: The Alpha 21264 microprocessor. IEEE Micro\u00a019, 24\u201336 (1999)","journal-title":"IEEE Micro"},{"key":"61_CR8","doi-asserted-by":"crossref","unstructured":"Burger, D., Goodman, J.R., Kagi, A.: Memory Bandwidth Limitations of Future Microprocessors. ISCA, 78\u201389 (1996)","DOI":"10.1145\/232973.232983"},{"key":"61_CR9","doi-asserted-by":"crossref","unstructured":"Chen, T.-F., Baer, J.-L.: A performance study of software and hardware data prefetching schemes. In: The 21st Annual International Symposium on Computer Architecture, pp. 223\u2013232 (1994)","DOI":"10.1109\/ISCA.1994.288147"},{"issue":"1","key":"61_CR10","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"W. Wulf","year":"1995","unstructured":"Wulf, W., McKee, S.: Hitting the Memory Wall: Implications of the Obvious. ACM Computer Architecture News\u00a023(1), 20\u201324 (1995)","journal-title":"ACM Computer Architecture News"},{"key":"61_CR11","unstructured":"IBM Microelectronics and Motorola Corporation, PowerPC Microprocessor Family: The Programming Environments, Motorola Inc., (1994)"},{"issue":"2","key":"61_CR12","doi-asserted-by":"publisher","first-page":"191","DOI":"10.1145\/173682.165154","volume":"21","author":"N. Jouppi","year":"1993","unstructured":"Jouppi, N.: Cache Write Policies and Performance. ACM SIGARCH Computer Architecture News\u00a021(2), 191\u2013201 (1993)","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"61_CR13","doi-asserted-by":"crossref","unstructured":"Henning, J.L.: SPEC CPU 2000: Measuring CPU Performance in the new millennium. IEEE Computer (July 2000)","DOI":"10.1109\/2.869367"},{"key":"61_CR14","unstructured":"Hu, S., John, L.: Avoiding Store Misses to Fully Modified Cache Blocks. Submitted to EURO-PAR (October 2005)"},{"key":"61_CR15","unstructured":"Huh, J., Burger, D., Keckler, S.: Exploring the design space of future CMPs. In: The 10th International Conference on Parallel Architectures and Compilation Techniques, September 2001, pp. 199\u2013210 (2001)"},{"key":"61_CR16","doi-asserted-by":"publisher","first-page":"22","DOI":"10.1109\/MC.2004.1273999","volume":"37","author":"D. Burger","year":"2004","unstructured":"Burger, D., Goodman, J.R.: Billion-transistor architectures: there and back again. Computer\u00a037, 22\u201328 (2004)","journal-title":"Computer"}],"container-title":["Lecture Notes in Computer Science","Advances in Computer Systems Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11572961_61.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T19:55:54Z","timestamp":1605642954000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11572961_61"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540296430","9783540321088"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/11572961_61","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}