{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:36:49Z","timestamp":1725550609422},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540296393"},{"type":"electronic","value":"9783540321071"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11573937_10","type":"book-chapter","created":{"date-parts":[[2005,10,15]],"date-time":"2005-10-15T07:19:03Z","timestamp":1129360743000},"page":"71-80","source":"Crossref","is-referenced-by-count":0,"title":["RIMP: Runtime Implicit Predication"],"prefix":"10.1007","author":[{"given":"YuXing","family":"Tang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kun","family":"Deng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"XiaoDong","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yong","family":"Dou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"XingMing","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"5","key":"10_CR1","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/40.877948","volume":"20","author":"H. Sharangpani","year":"2000","unstructured":"Sharangpani, H., Aurora, K.: Itanium processor microarchitecture. IEEE Micro\u00a020(5), 24\u201343 (2000)","journal-title":"IEEE Micro"},{"key":"10_CR2","unstructured":"Chuang, W., Calder, B., Ferrante, J.: Phi-Predication for Light-Weight If-Conversion. In: Proceedings of the Intl. Symposium on code generation and optimization, March 2003, pp. 179\u2013190 (2003)"},{"key":"10_CR3","doi-asserted-by":"crossref","unstructured":"Sias, J., Hunter, H., Hwu, W.: Enhancing loop buffering of media and telecommunication applications using low-overhead predication. In: Proceedings of the 34th MICRO (December 2001)","DOI":"10.1109\/MICRO.2001.991124"},{"key":"10_CR4","doi-asserted-by":"publisher","first-page":"37","DOI":"10.1145\/339647.339653","volume-title":"Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA-00)","author":"Q. Jacobson","year":"2000","unstructured":"Jacobson, Q., Smith, J.E.: Trace preconstruction. In: Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA-2000), pp. 37\u201346. IEEE Computer Society Press, Vancouver (2000)"},{"key":"10_CR5","first-page":"24","volume-title":"Proceedings of the 29th MICRO","author":"E. Rotenberg","year":"1996","unstructured":"Rotenberg, E., Bennett, S., Smith, J.E.: Trace cache: a low latency approach to high bandwidth instruction fetching [A]. In: Proceedings of the 29th MICRO, pp. 24\u201335. IEEE Computer Society Press, Los Alamitos (1996)"},{"key":"10_CR6","volume-title":"Alpha AXP Architecture Reference Manual","author":"R.L. Sites","year":"1995","unstructured":"Sites, R.L., Witek, R.T.: Alpha AXP Architecture Reference Manual, 2nd edn. Digital Press, Boston (1995)","edition":"2"},{"key":"10_CR7","unstructured":"Sohm, O.: Variable-Length Decding on the TMS320C6000 DSP platform. Application Report (June 2002), http:\/\/www-s.ti.com\/sc\/psheets\/spra805\/spra805.pdf"},{"key":"10_CR8","doi-asserted-by":"crossref","unstructured":"Mahlke, S.A., Lin, D.C., Chen, W.Y., Hank, R.E., Bringmann, R.A.: Effective Compiler Support for Predicated Execution Using the Hyperblock. In: 25th Intl. Conf. On Microarchitecture, December 1992, pp. 45\u201354 (1992)","DOI":"10.1109\/MICRO.1992.696999"},{"key":"10_CR9","unstructured":"Gwennap, L.: Intel\u2019s P6 uses ducoupled superscalar Design. Microprocessor Report\u00a09(2) (February 1995)"},{"key":"10_CR10","unstructured":"Hyper-pipelined technology: Intel Pentium 4 Processor \u2013 Product Overview (2004), http:\/\/www.intel.com\/designPentium4\/prodbref\/"},{"issue":"6","key":"10_CR11","doi-asserted-by":"publisher","first-page":"12","DOI":"10.1109\/40.888700","volume":"20","author":"M. Tremblay","year":"2000","unstructured":"Tremblay, M., Chan, J., Chaudhry, S., Conigliaro, A.W., Tse, S.S.: The MAJC Architecture: A Synthesis of Parallelism and Scalability. IEEE Micro\u00a020(6), 12\u201325 (2000)","journal-title":"IEEE Micro"},{"key":"10_CR12","unstructured":"Krewell, K.: Alhpa ev7 processor: a high-performance tradition continues. Microprocessor Report. In-Stat\/MDR (April 2002)"},{"key":"10_CR13","doi-asserted-by":"crossref","unstructured":"Pnevmatikatos, D.N., Sohi, G.S.: Guarded Execution and Branch Prediction in Dynamic ILP processors. In: 21st Intl. Symp. on computer architecture, June 1994, pp. 120\u2013129 (1994)","DOI":"10.1109\/ISCA.1994.288156"},{"key":"10_CR14","doi-asserted-by":"crossref","unstructured":"Mahlke, S.A., Hank, R.E., Bringmann, R.A., Gyllenhaal, J.C., Gallagher, D.M., Hwu, W.: Characterizing the Impact of Predicated Execution on Branch Prediction. In: 27th Annual Intl. Symp. On Microarchitecture, San Jose, CA (December 1994)","DOI":"10.1145\/192724.192755"},{"key":"10_CR15","doi-asserted-by":"crossref","unstructured":"Tyson, G.S.: The Effects of Predicated Execution on Branch Prediction. In: 27th Annual Intl. Symp. On Microarchitecture, San Jose, CA, December 1994, pp. 196\u2013206 (1994)","DOI":"10.1145\/192724.192753"},{"issue":"1","key":"10_CR16","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/2.19820","volume":"22","author":"R. Rau","year":"1989","unstructured":"Rau, R., Yen, D., Yen, W., Towle, R.: The Cydra 5 Departmental Supercomputer. IEEE Computer\u00a022(1), 12\u201335 (1989)","journal-title":"IEEE Computer"},{"key":"10_CR17","doi-asserted-by":"crossref","unstructured":"Klauser, A., Austin, T., Grunwald, D., Calder, B.: Dynamic Hammock Predication for Non-predicated Instruction Set Architectures. In: Proceedings of ICPACT (1998)","DOI":"10.1109\/PACT.1998.727261"},{"key":"10_CR18","doi-asserted-by":"crossref","unstructured":"Chang, P.Y., Hao, E., Patt, Y., Chang, P.: Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution. In: Intl. Conf. On Parallel Arch. And Compilation Techniques, Limassol, Cyprus (June 1995)","DOI":"10.1007\/BF03356749"},{"key":"10_CR19","doi-asserted-by":"crossref","unstructured":"Aramon, J.L., Gonzalez, J., Gonzalez, A., Smith, J.E.: Dual path instruction processing. In: Proceeding of the 16th Intl. Conf. On Supercomputing, New York (2002)","DOI":"10.1145\/514191.514223"},{"issue":"2","key":"10_CR20","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1109\/2.982917","volume":"35","author":"T. Austin","year":"2002","unstructured":"Austin, T., Larson, E., Ernst, D.: SimpleScalar: an infrastructure for computer system modeling. IEEE computer\u00a035(2), 59\u201367 (2002)","journal-title":"IEEE computer"}],"container-title":["Lecture Notes in Computer Science","Advanced Parallel Processing Technologies"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11573937_10.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T14:56:39Z","timestamp":1605624999000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11573937_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540296393","9783540321071"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/11573937_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}