{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,5]],"date-time":"2025-01-05T05:23:29Z","timestamp":1736054609507,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":23,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540297697"},{"type":"electronic","value":"9783540321002"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11576235_26","type":"book-chapter","created":{"date-parts":[[2005,10,18]],"date-time":"2005-10-18T15:32:46Z","timestamp":1129649566000},"page":"205-215","source":"Crossref","is-referenced-by-count":0,"title":["Cache Management for Discrete Processor Architectures"],"prefix":"10.1007","author":[{"given":"Jih-Fu","family":"Tu","sequence":"first","affiliation":[]}],"member":"297","reference":[{"key":"26_CR1","doi-asserted-by":"crossref","unstructured":"Acacio, M.E., Gonzalez, J., Garcia, J.M., Duato, J.: A. novel approach to reduce L2 miss latency in shared-memory multiprocessors. In: Proceedings International on Parallel and Distributed Processing Symposium, IPDPS 2002, April 15-19, pp. 62\u201369 (2002) Abstracts and CD-ROM","DOI":"10.1109\/IPDPS.2002.1015554"},{"key":"26_CR2","doi-asserted-by":"crossref","unstructured":"Allen, M.S., Lewchuk, W.K., Coddington, J.D.: A high performance bus and cache controller for PowerPC multiprocessing systems. In: Proceedings 1995 IEEE International Conference on Computer Design: VLSI in Computers and Processors 1995, ICCD 1995, October 2-4, pp. 204\u2013211 (1995)","DOI":"10.1109\/ICCD.1995.528811"},{"key":"26_CR3","doi-asserted-by":"crossref","unstructured":"Chaudhry, G.M., Han, W.: Separated caches and buses for multiprocessor system. In: Proceedings of the 36th Midwest Symposium on Circuits and Systems, August 16-18, vol.\u00a02, pp. 1113\u20131116 (1993)","DOI":"10.1109\/MWSCAS.1993.343282"},{"key":"26_CR4","unstructured":"Chen, Y.-Y., Peir, J.-K., King, C.-T.: Performance of shared cache on multithreaded architectures. In: Proceedings of the Fourth Euromicro Workshop on Parallel and Distributed, Janaury 24-26, pp. 541\u2013548 (1996)"},{"issue":"2","key":"26_CR5","doi-asserted-by":"publisher","first-page":"97","DOI":"10.1109\/71.577249","volume":"8","author":"Q. Chunming","year":"1997","unstructured":"Chunming, Q., Melhem, R.: Reducing communication latency with path multiplexing in optically interconnected multiprocessor systems. IEEE Transactions on Parallel and Distributed Systems\u00a08(2), 97\u2013108 (1997)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"26_CR6","doi-asserted-by":"crossref","unstructured":"Foglia, P., Giorgi, R., Prete, C.A.: Analysis of sharing overhead in shared memory multiprocessors. In: Proceedings of the Thirty-First Hawaii International Conference, Janaury 6-9, vol.\u00a07, pp. 776\u2013777 (1998)","DOI":"10.1109\/HICSS.1998.649284"},{"key":"26_CR7","doi-asserted-by":"crossref","unstructured":"Hsieh, D., Feipei, L.: Design and test of memory management unit and cache controller chip. In: Proceedings. IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering. TENCON 1993, October 19-21, pp. 10\u201313 (1993)","DOI":"10.1109\/TENCON.1993.319916"},{"key":"26_CR8","doi-asserted-by":"crossref","unstructured":"Ivanov, L., Nunna, R.: Modeling and verification of cache coherence Protocols. In: The 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, May 6-9, pp. 129\u2013132 (2001)","DOI":"10.1109\/ISCAS.2001.922002"},{"key":"26_CR9","doi-asserted-by":"crossref","unstructured":"Jie, T., Schulz, M., Karl, W.: A simulation tool for evaluating shared memory systems. In: 36th Annual Simulation Symposium, March 30-April 2, pp. 335\u2013342 (2003)","DOI":"10.1109\/SIMSYM.2003.1192831"},{"key":"26_CR10","unstructured":"Kang, J.-W., Rim, K.-W.: VLSI implementation of multiprocessor system. In: IEEE Region 10 International Conference on Microelectronics and VLSI, TENCON 1995, November 6-10, pp. 480\u2013483 (1995)"},{"issue":"7","key":"26_CR11","doi-asserted-by":"publisher","first-page":"960","DOI":"10.1109\/TC.2003.1214343","volume":"52","author":"D. Keen","year":"2003","unstructured":"Keen, D., Oskin, M., Hensley, J., Chong, F.T.: Cache coherence in intelligent memory systems. IEEE Transactions on Computers\u00a052(7), 960\u2013966 (2003)","journal-title":"IEEE Transactions on Computers"},{"key":"26_CR12","doi-asserted-by":"crossref","unstructured":"Nikhil, R.S., Arvind: Can Dataflow Subsume von Neumann Computing. In: Proc. 16th Annu. Int. Symposium. Computer Architecture, pp. 262\u2013272 (1989)","DOI":"10.1109\/ISCA.1989.714561"},{"key":"26_CR13","doi-asserted-by":"crossref","unstructured":"Nikhil, R.S., Papadopulos, G.M.: *T: A Multithreaded Massively Parallel Architecture. In: Proc. 19th Annual Int. Symposium Computer Architecture, May 1992, pp. 361\u2013372 (1992)","DOI":"10.1145\/139669.139715"},{"key":"26_CR14","doi-asserted-by":"crossref","unstructured":"Nayfeh, B.A., Olukotun, K., Singh, J.P.: The impact of shared-cache clustering in small-scale shared-memory multiprocessors. In: Proceedings Second International Symposium on High-Performance Computer Architecture, Febraury 3-7, pp. 74\u201384 (1996)","DOI":"10.1109\/HPCA.1996.501175"},{"key":"26_CR15","doi-asserted-by":"crossref","unstructured":"Reisner, J.A., Wailes, T.S.: A cache coherency protocol for optically connected parallel computer systems. In: Proceedings of Second International Symposium on High-Performance Computer Architecture, February 3-7, pp. 222\u2013231 (1996)","DOI":"10.1109\/HPCA.1996.501188"},{"key":"26_CR16","doi-asserted-by":"crossref","unstructured":"Sahuquillo, J., Pont, A.: Impact of reducing miss write latencies in multiprocessors with two level cache. In: Proceedings 24th Euromicro Conference, August 25-27, vol.\u00a01, pp. 333\u2013336 (1998)","DOI":"10.1109\/EURMIC.1998.711822"},{"key":"26_CR17","unstructured":"Sawchuk, A.A., Cheng, L.: Considerations for optoelectronic shared cache parallel computers. In: Proceedings of the First International Workshop on Massively Parallel Processing Using Optical Interconnections, April 26-27, pp. 241\u2013251 (1994)"},{"key":"26_CR18","unstructured":"Scientific and Engineering Software, inc., SES\/workbench User\u2019s Manual, Release 2.1 Scientific and Engineering Software Austin, TX, USA, 2 (1992)"},{"key":"26_CR19","doi-asserted-by":"crossref","unstructured":"Selvakumar, S., Prabhakar, P.: Implementation and comparison of distributed caching schemes. In: Proceedings of the IEEE International Conference on Networks (ICON 2000), September 5-8, p. 491 (2000)","DOI":"10.1109\/ICON.2000.875842"},{"key":"26_CR20","doi-asserted-by":"crossref","unstructured":"Shalan, M., Mooney, V.J.: Hardware support for real-time embedded multiprocessor system-on-a-chip memory management. In: Proceedings of the Tenth International Symposium on Hardware\/Software Codesign, CODES 2002, May 6-8, pp. 79\u201384 (2002)","DOI":"10.1145\/774789.774806"},{"issue":"9","key":"26_CR21","doi-asserted-by":"publisher","first-page":"881","DOI":"10.1109\/12.795219","volume":"48","author":"J.-Y. Tsai","year":"1999","unstructured":"Tsai, J.-Y., Huang, J., Amlo, C., Lilja, D.J., Yew, P.-C.: The superthreaded processor architecture. IEEE Transactions on Computers\u00a048(9), 881\u2013902 (1999)","journal-title":"IEEE Transactions on Computers"},{"issue":"5","key":"26_CR22","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1049\/ip-cdt:20020426","volume":"149","author":"J.-F. Tu","year":"2002","unstructured":"Tu, J.-F.: SMTA: A Next Generational High Performance Multithreaded Architecture. IEE Proceedings- Computer and Digital Techniques\u00a0149(5), 213\u2013218 (2002)","journal-title":"IEE Proceedings- Computer and Digital Techniques"},{"issue":"1","key":"26_CR23","first-page":"204","volume":"74","author":"Y. Yamaguchi","year":"1991","unstructured":"Yamaguchi, Y., Sakai, S., Kodama, Y.: Synchronization Mechanism of a Highly Parallel Dataflow Machine EM-4. IEICE Transactions\u00a074(1), 204\u2013213 (1991)","journal-title":"IEICE Transactions"}],"container-title":["Lecture Notes in Computer Science","Parallel and Distributed Processing and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11576235_26.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,5]],"date-time":"2025-01-05T00:52:24Z","timestamp":1736038344000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11576235_26"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540297697","9783540321002"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/11576235_26","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}