{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T16:10:01Z","timestamp":1736611801091,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540309369"},{"type":"electronic","value":"9783540324270"}],"license":[{"start":{"date-parts":[[2005,1,1]],"date-time":"2005-01-01T00:00:00Z","timestamp":1104537600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2005]]},"DOI":"10.1007\/11602569_53","type":"book-chapter","created":{"date-parts":[[2006,10,17]],"date-time":"2006-10-17T23:57:31Z","timestamp":1161129451000},"page":"518-527","source":"Crossref","is-referenced-by-count":0,"title":["Integrating a New Cluster Assignment and Scheduling Algorithm into an Experimental Retargetable Code Generation Framework"],"prefix":"10.1007","author":[{"given":"K. Vasanta","family":"Lakshmi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deepak","family":"Sreedhar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Easwaran","family":"Raman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Priti","family":"Shankar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"53_CR1","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1016\/S0304-3975(98)00205-9","volume":"242","author":"P. Shankar","year":"2000","unstructured":"Shankar, P., Gantait, A., Yuvaraj, A.R., Madhavan, M.: A New Algorithm For Linear Regular Tree Pattern Matching. Theoretical Computer Science\u00a0242, 125\u2013142 (2000)","journal-title":"Theoretical Computer Science"},{"key":"53_CR2","unstructured":"Sreedhar, D., Easwaran, R.: Retargetable code generation for clustered embedded processors, ME Project Report. Dept of CSA, Indian Institute of Science"},{"key":"53_CR3","doi-asserted-by":"crossref","unstructured":"Chaitin, G.J.: Register Allocation and Spilling via Graph Coloring. In: Proceedings of the 1982 Symposium on Compiler Construction, June 1982, pp. 98\u2013105 (1982)","DOI":"10.1145\/800230.806984"},{"issue":"3","key":"53_CR4","doi-asserted-by":"publisher","first-page":"428","DOI":"10.1145\/177492.177575","volume":"16","author":"P. Briggs","year":"1994","unstructured":"Briggs, P., Cooper, K., Torczon, L.: Improvements to Graph Coloring Register Allocation. ACM Transactions on Programming Languages and Systems\u00a016(3), 428\u2013455 (1994)","journal-title":"ACM Transactions on Programming Languages and Systems"},{"key":"53_CR5","doi-asserted-by":"crossref","unstructured":"Proebsting, T.A., Fraser, C.W.: Detecting Pipeline Hazards Quickly. In: 21st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (January 1994)","DOI":"10.1145\/174675.177904"},{"key":"53_CR6","unstructured":"Texas Instruments TMS320C6000 CPU and Instruction Set Reference Guide"},{"key":"53_CR7","unstructured":"Leupers, R.: Instruction Scheduling for Clustered VLIW DSPs. In: Proceedings of the International Conference on Parallel Architecture and Compilation Techniques, Philadelphia, PA (October 2000)"},{"key":"53_CR8","doi-asserted-by":"publisher","first-page":"229","DOI":"10.1007\/BF01205185","volume":"7","author":"W.-m. Hwu","year":"1993","unstructured":"Hwu, W.-m.: The superblock: An effective structure for VLIW and superscalar compilation. The Journal of Supercomputing\u00a07, 229\u2013248 (1993)","journal-title":"The Journal of Supercomputing"},{"key":"53_CR9","volume-title":"Principles of Compiler Design","author":"A.V. Aho","year":"1977","unstructured":"Aho, A.V., Ullman, J.D.: Principles of Compiler Design. Addison-Wesley, Reading (1977)"},{"key":"53_CR10","doi-asserted-by":"crossref","unstructured":"Kailas, K., Ebcioglu, K., Agrawala, A.: CARS: A New Code Generation Framework for Clustered ILP Processors. In: 7th Interbational SYmposium on High Performance Computer Architecture, pp. 133\u2013143 (2001)","DOI":"10.1109\/HPCA.2001.903258"},{"issue":"6","key":"53_CR11","doi-asserted-by":"publisher","first-page":"973","DOI":"10.1145\/371880.371881","volume":"22","author":"M. Madhavan","year":"2000","unstructured":"Madhavan, M., Shankar, P., Rai, S., Ramakrishna, U.: Extending Graham-Glanville techniques for optimal code generation. ACM Trans. Program. Lang. Syst.\u00a022(6), 973\u20131001 (2000)","journal-title":"ACM Trans. Program. Lang. Syst."},{"key":"53_CR12","unstructured":"http:\/\/dspvillage.ti.com\/docs\/catalog\/devtools\/details.jhtml?templateId=5121&path=templatedata\/cm\/tooldetail\/data\/ccs_codegen"},{"key":"53_CR13","unstructured":"Lee, W., Puppin, D., Swenson, S., Amarasinghe, S.: Convergent Scheduling. In: MICRO-35, Istanbul, Turkey (November 2002)"},{"key":"53_CR14","doi-asserted-by":"crossref","unstructured":"Capitanio, A., Dutt, N., Nicolau, A.: Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeos. In: 25th International Symposium on Microarchitecture, MICRO (1992)","DOI":"10.1145\/144965.145839"},{"key":"53_CR15","volume-title":"Bulldog: A Compiler for VLIW Architectures","author":"J.R. Ellis","year":"1986","unstructured":"Ellis, J.R.: Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge (1986)"},{"key":"53_CR16","unstructured":"Kailas, K., Ebcioglu, K., Agrawala, A.K.: CARS: A New Code Generation Framework for Clustered ILP Processors. In: 7th International Symposium on High Performance Computer Architecture (HPCA)"},{"key":"53_CR17","unstructured":"Ozer, E., Banerjia, S., Conte, T.M.: Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. In: 31st International Symposium on Microarchitecture (MICRO)"},{"key":"53_CR18","unstructured":"Desoli, G.: Instruction Assignment for Clustered VLIW DSP Compilers: a New Approach. Technical Report HPL-98-13, Hewlett Packard Laboratories (1998)"},{"key":"53_CR19","unstructured":"The Impact Research Group, University of Urbana Champaign., http:\/\/www.crhc.uiuc.edu\/Impact"},{"key":"53_CR20","unstructured":"Trimaran Compiler, http:\/\/www.trimaran.org"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing \u2013 HiPC 2005"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11602569_53","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T15:50:28Z","timestamp":1736610628000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11602569_53"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005]]},"ISBN":["9783540309369","9783540324270"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/11602569_53","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2005]]}}}