{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,8]],"date-time":"2025-01-08T05:41:24Z","timestamp":1736314884409,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540327653"},{"type":"electronic","value":"9783540327660"}],"license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11682127_12","type":"book-chapter","created":{"date-parts":[[2006,2,14]],"date-time":"2006-02-14T12:53:08Z","timestamp":1139921588000},"page":"160-175","source":"Crossref","is-referenced-by-count":0,"title":["A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering"],"prefix":"10.1007","author":[{"given":"Woo-Chan","family":"Park","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Duk-Ki","family":"Yoon","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kil-Whan","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Il-San","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyung-Su","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Won-Jong","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tack-Don","family":"Han","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung-Bong","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"11","key":"12_CR1","doi-asserted-by":"publisher","first-page":"1775","DOI":"10.1109\/4.962301","volume":"36","author":"A.K. Khan","year":"2001","unstructured":"Khan, A.K., et al.: A 150-MHz graphics rendering processor with 256-Mb embedded DRAM. IEEE Journal of Solid-State Circuits\u00a036(11), 1775\u20131783 (2001)","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"4","key":"12_CR2","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1109\/38.291528","volume":"14","author":"S. Molnar","year":"1994","unstructured":"Molnar, S., Cox, M., Ellsworth, M., Fuchs, H.: A sorting classification of parallel rendering. IEEE Computer Graphics and Applications\u00a014(4), 23\u201332 (1994)","journal-title":"IEEE Computer Graphics and Applications"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Nishimura, S., Kunii, T.: VC-1: A scalable graphics computer with virtual local frame buffers. In: Proc. of SIGGRAPH 1996, pp. 365\u2013372 (August 1996)","DOI":"10.1145\/237170.237275"},{"key":"12_CR4","doi-asserted-by":"crossref","unstructured":"Deering, M., Naegle, D.: The SAGE Architecture. In: Proc. of SIGGRAPH 2002, pp. 683\u2013692 (July 2002)","DOI":"10.1145\/566654.566638"},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Wittenbrink, G.M.: R-buffer: A pointerless A-buffer hardware architecture. In: Proc. SIGGRAPH\/Eurographics Workshop on Graphics Hardware, pp. 73\u201380 (August 2001)","DOI":"10.1145\/383507.383529"},{"key":"12_CR6","doi-asserted-by":"crossref","unstructured":"Aila, T., Miettinen, V., Nordlund, P.: Delay streams for graphics hardware. In: Proc. SIGGRAPH 2003, pp. 792\u2013880 (August 2003)","DOI":"10.1145\/1201775.882347"},{"key":"12_CR7","doi-asserted-by":"crossref","unstructured":"Carpenter, L.: The A-Buffer, an antialiased hidden surface method. In: Proc. SIGGRAPH, pp. 103\u2013108 (1984)","DOI":"10.1145\/800031.808585"},{"issue":"11","key":"12_CR8","doi-asserted-by":"publisher","first-page":"1501","DOI":"10.1109\/TC.2003.1244948","volume":"52","author":"W.-C. Park","year":"2003","unstructured":"Park, W.-C., Lee, K.-W., Kim, I.-S., Han, T.-D., Yang, S.-B.: An effective pixel rasterization pipeline architecture for 3D rendering processors. IEEE Transactions on Computers\u00a052(11), 1501\u20131508 (2003)","journal-title":"IEEE Transactions on Computers"},{"key":"12_CR9","doi-asserted-by":"crossref","unstructured":"Michael, F.D., Stephen, A.S., Michael, G.L.: FBRAM: A new form memory optimized for 3D Graphics. In: Proc SIGGRAPH 1994, pp. 167\u2013174 (1994)","DOI":"10.1145\/192161.192194"},{"issue":"12","key":"12_CR10","doi-asserted-by":"publisher","first-page":"1563","DOI":"10.1109\/4.482207","volume":"30","author":"K. Inoue","year":"1995","unstructured":"Inoue, K., Nakamura, H., Kawai, H.: A 10b Frame buffer memory with Z-compare and A-bending units. IEEE Journal of Solid-State Circuits\u00a030(12), 1563\u20131568 (1995)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"12_CR11","unstructured":"McCormack, J., McNamara, H., Gianos, C., Seiler, L., Jouppi, N.P., Correl, K., Dutton, T., Zurawski, J.: Neon: A (big) (fast) single-chip 3D workstation graphics accelerator, Research Report 98\/1, Western Research Laboratory, Compaq Corporation (August 1998) (revised, July 1999)"},{"key":"12_CR12","doi-asserted-by":"crossref","unstructured":"Hill, M.D., Larus, J.R., Lebeck, A.R., Talluri, M., Wood, D.A.: Wisconsin architectural research tool set. In: ACM SIGARCH Computer Architecture News, vol.\u00a021, pp. 8\u201310 (September 1993)","DOI":"10.1145\/165496.165500"},{"key":"12_CR13","volume-title":"Computer organization & design: The hardware\/software interface","author":"D.A. Patterson","year":"1998","unstructured":"Patterson, D.A., Hennessy, J.L.: Computer organization & design: The hardware\/software interface, 2nd edn. Morgan Kaufmann Publisher Inc., San Francisco (1998)","edition":"2"},{"key":"12_CR14","unstructured":"http:\/\/www.idsoftware.com\/games\/quake\/quake3-arena"},{"key":"12_CR15","unstructured":"http:\/\/www.spec.org\/gpc\/opc.static\/opcview70.html"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems - ARCS 2006"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11682127_12","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,7]],"date-time":"2025-01-07T18:49:40Z","timestamp":1736275780000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11682127_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540327653","9783540327660"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/11682127_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}