{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,8]],"date-time":"2025-01-08T23:10:28Z","timestamp":1736377828314,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540340775"},{"type":"electronic","value":"9783540340782"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11751632_67","type":"book-chapter","created":{"date-parts":[[2006,5,11]],"date-time":"2006-05-11T15:00:57Z","timestamp":1147359657000},"page":"612-621","source":"Crossref","is-referenced-by-count":0,"title":["An Efficient Delay Metric on RC Interconnects Under Saturated Ramp Inputs"],"prefix":"10.1007","author":[{"given":"Ki-Young","family":"Kim","sequence":"first","affiliation":[]},{"given":"Seung-Yong","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Seok-Yoon","family":"Kim","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"67_CR1","doi-asserted-by":"publisher","first-page":"1507","DOI":"10.1109\/43.664231","volume":"16","author":"A.B. Kahng","year":"1997","unstructured":"Kahng, A.B., Muddu, S.: An analytical delay model for RLC interconnects. IEEE Trans. Computer-Aided Design\u00a016, 1507\u20131514 (1997)","journal-title":"IEEE Trans. Computer-Aided Design"},{"key":"67_CR2","doi-asserted-by":"crossref","unstructured":"Kay, R., Pileggi, L.T.: PRIMO: Probability interpretation of moments for delay calculation. In: Proc. IEEE\/ACM Design Automation Conference, June 1998, pp. 463\u2013468 (1998)","DOI":"10.1145\/277044.277172"},{"key":"67_CR3","doi-asserted-by":"crossref","unstructured":"Lin, T., Acar, E., Pileggi, L.T.: h-gamma: An RC delay metric based on a gamma distribution approximation to the homogeneous response. In: Proc. IEEE\/ACM Int. Conf. Computer-Aided Design, November 1998, pp. 19\u201325 (1998)","DOI":"10.1145\/288548.288555"},{"key":"67_CR4","doi-asserted-by":"publisher","first-page":"571","DOI":"10.1109\/43.920682","volume":"20","author":"C.J. Alpert","year":"2001","unstructured":"Alpert, C.J., Devgan, A., Kashyap, C.: RC Delay Metrics for Performance Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a020, 571\u2013582 (2001)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"67_CR5","doi-asserted-by":"crossref","unstructured":"Menezes, N., Pullela, S., Dartu, F., Pillage, L.T.: RC Interconnect Synthesis - A Moment Fitting Approach. In: Proc. IEEE\/ACM Intl. Conf. Computer-Aided Design, November 1994, pp. 418\u2013425 (1994)","DOI":"10.1109\/ICCAD.1994.629837"},{"key":"67_CR6","doi-asserted-by":"crossref","unstructured":"Kahng, A.B., Muddu, S.: Analysis of RC Interconnections Under Ramp Input. UCLA CS Dept. TR-960013 (April 1996)","DOI":"10.1145\/240518.240619"},{"key":"67_CR7","doi-asserted-by":"crossref","unstructured":"Kashyap, C.V., Alpert, C.J., Liu, F., Devgan, A.: Closed Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs. In: ACM\/SIGDA 2003 International Symposium on Physical Design (April 2003)","DOI":"10.1145\/640000.640009"},{"key":"67_CR8","doi-asserted-by":"crossref","unstructured":"O\u2019Brien, P.R., Savarino, T.L.: Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation. In: Proc. IEEE\/ACM Int. Conf. Computer-Aided Design, November 1989, pp. 512\u2013515 (1989)","DOI":"10.1109\/ICCAD.1989.77002"},{"key":"67_CR9","doi-asserted-by":"crossref","unstructured":"Qian, J., Pullela, S., Pillage, L.T.: Modeling the \u201cEffective Capacitance\u201d for the RC Interconnect of CMOS Gates. IEEE Trans. on Computer-Aided Design of Integrated Circuits and System\u00a013(12) (December 1994)","DOI":"10.1109\/43.331409"},{"key":"67_CR10","doi-asserted-by":"crossref","unstructured":"Kahng, A.B., Muddu, S.: Efficient Gate Delay Modeling for Large Interconnect Loads. In: IEEE Multi-Chip Module Conf. (February 1996)","DOI":"10.1109\/MCMC.1996.510795"},{"key":"67_CR11","doi-asserted-by":"crossref","unstructured":"Gupta, R., Tutuianu, B., Pileggi, L.T.: The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. In: ACM\/IEEE Design Automation Conference, June 1995, pp. 364\u2013369 (1995)","DOI":"10.1145\/217474.217556"},{"key":"67_CR12","doi-asserted-by":"publisher","first-page":"202","DOI":"10.1109\/TCAD.1983.1270037","volume":"2","author":"J. Rubinstein","year":"1983","unstructured":"Rubinstein, J., Penfield Jr., P., Horowitz, M.A.: Signal delay in RC tree networks. IEEE Trans. on Computer Aided Design\u00a02, 202\u2013211 (1983)","journal-title":"IEEE Trans. on Computer Aided Design"},{"key":"67_CR13","doi-asserted-by":"crossref","unstructured":"Ratzlaff, C.L., Gopal, N., Pillage, L.T.: RICE: Rapid interconnect circuit evaluator. In: Proc. IEEE\/ACM Design Automation Conf., June 1991, pp. 555\u2013560 (1991)","DOI":"10.1145\/127601.127732"}],"container-title":["Lecture Notes in Computer Science","Computational Science and Its Applications - ICCSA 2006"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11751632_67.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,8]],"date-time":"2025-01-08T22:36:59Z","timestamp":1736375819000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11751632_67"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540340775","9783540340782"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/11751632_67","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}