{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T23:10:56Z","timestamp":1742944256167,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540367086"},{"type":"electronic","value":"9783540368632"}],"license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11802839_31","type":"book-chapter","created":{"date-parts":[[2006,8,2]],"date-time":"2006-08-02T20:08:58Z","timestamp":1154549338000},"page":"230-242","source":"Crossref","is-referenced-by-count":4,"title":["A Reconfigurable Data Cache for Adaptive Processors"],"prefix":"10.1007","author":[{"given":"D.","family":"Benitez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. C.","family":"Moure","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D. I.","family":"Rexachs","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Luque","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"10","key":"31_CR1","doi-asserted-by":"publisher","first-page":"1243","DOI":"10.1109\/TC.2003.1234523","volume":"52","author":"R. Balasubramonian","year":"2003","unstructured":"Balasubramonian, R., Albonesi, D., Buyuktosunoglu, A., Dwarkadas, S.: A Dynamically Tunable Memory Hierarchy. IEEE Tran. Computers\u00a052(10), 1243\u20131257 (2003)","journal-title":"IEEE Tran. Computers"},{"key":"31_CR2","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"363","DOI":"10.1007\/11602569_39","volume-title":"High Performance Computing \u2013 HiPC 2005","author":"D. Benitez","year":"2005","unstructured":"Benitez, D., Moure, J.C., Rexachs, D.I., Luque, E.: Performance and Power Evaluation of an Intelligently Adaptive Data Cache. In: Bader, D.A., Parashar, M., Sridhar, V., Prasanna, V.K. (eds.) HiPC 2005. LNCS, vol.\u00a03769, pp. 363\u2013375. Springer, Heidelberg (2005)"},{"issue":"3","key":"31_CR3","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1145\/268806.268810","volume":"25","author":"D. Burger","year":"1997","unstructured":"Burger, D., Austin, T.M.: The SimpleScalar Toolset, Ver. 2.0. Computer Architecture News\u00a025(3), 13\u201325 (1997)","journal-title":"Computer Architecture News"},{"key":"31_CR4","first-page":"233","volume-title":"Proc. 29th Intl. Symp. Computer Architecture","author":"A.S. Dhodapkar","year":"2002","unstructured":"Dhodapkar, A.S., Smith, J.E.: Managing Multi-Configuration Hardware via Dynamic Working Set Analysis. In: Proc. 29th Intl. Symp. Computer Architecture, pp. 233\u2013244. IEEE Computer Society, Los Alamitos (2002)"},{"key":"31_CR5","doi-asserted-by":"crossref","unstructured":"Epalza, M., Ienne, P., Mlynek, D.: Adding limited reconfigurability to superscalar processors. In: Proc. 13th Intl. Conf. on PACT, pp. 53\u201362 (2004)","DOI":"10.1109\/PACT.2004.1342541"},{"key":"31_CR6","first-page":"157","volume-title":"Proc. 30th Intl. Symp. Computer Architecture","author":"M.C. Huang","year":"2003","unstructured":"Huang, M.C., Renau, J., Torrellas, J.: Positional Adaptation of Processors: Application to Energy Reduction. In: Proc. 30th Intl. Symp. Computer Architecture, pp. 157\u2013168. IEEE Computer Society, Los Alamitos (2003)"},{"key":"31_CR7","first-page":"211","volume-title":"Proc. 10th Intl. Conf. Architectural Support for Program. Languages and Operating Syst.","author":"C. Kim","year":"2002","unstructured":"Kim, C., Burger, D., Keckler, S.W.: An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches. In: Proc. 10th Intl. Conf. Architectural Support for Program. Languages and Operating Syst., pp. 211\u2013222. ACM Press, New York (2002)"},{"issue":"4","key":"31_CR8","doi-asserted-by":"publisher","first-page":"388","DOI":"10.1109\/34.206958","volume":"15","author":"C. Lee","year":"1993","unstructured":"Lee, C., Landgrebe, D.A.: Feature Extraction Based On Decision Boundaries. IEEE Tran. Pattern Analysis and Machine Intelligence\u00a015(4), 388\u2013400 (1993)","journal-title":"IEEE Tran. Pattern Analysis and Machine Intelligence"},{"key":"31_CR9","first-page":"214","volume-title":"Proc. 27th Intl. Symp. Computer Architecture","author":"P. Ranganathan","year":"2000","unstructured":"Ranganathan, P., Adve, S., Jouppi, N.P.: Reconfigurable Caches and their Application to Media Processing. In: Proc. 27th Intl. Symp. Computer Architecture, pp. 214\u2013224. ACM Press, New York (2000)"},{"key":"31_CR10","first-page":"29","volume-title":"Proc. 8th Symp. High Performance Computer Architecture","author":"G. Semeraro","year":"2002","unstructured":"Semeraro, G., et al.: Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. In: Proc. 8th Symp. High Performance Computer Architecture, pp. 29\u201340. IEEE Computer Society, Los Alamitos (2002)"},{"key":"31_CR11","first-page":"45","volume-title":"Proc. Intl. Conf. on ASPLOS","author":"T. Sherwood","year":"2002","unstructured":"Sherwood, T., Perelman, E., Hamerly, G., Calder, B.: Automatically Characterizing Large Scale Programs. In: Proc. Intl. Conf. on ASPLOS, pp. 45\u201357. ACM Press, New York (2002)"},{"key":"31_CR12","first-page":"336","volume-title":"Proc. 30th Intl. Symp. Computer Architecture","author":"T. Sherwood","year":"2003","unstructured":"Sherwood, T., Sair, S., Calder, B.: Phase Tracking and Prediction. In: Proc. 30th Intl. Symp. Computer Architecture, pp. 336\u2013349. ACM Press, New York (2003)"},{"key":"31_CR13","unstructured":"Shivakumar, P., Jouppi, N.P.: CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. Compact WRL Technical Report 2001\/2 (2001)"},{"key":"31_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"275","DOI":"10.1007\/3-540-44687-7_29","volume-title":"Field-Programmable Logic and Applications","author":"S. Vassiliadis","year":"2001","unstructured":"Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN coded processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol.\u00a02147, pp. 275\u2013285. Springer, Heidelberg (2001)"},{"key":"31_CR15","doi-asserted-by":"crossref","unstructured":"Zhang, C., Vahid, F., Najjar, W.: A Highly Configurable Cache Architecture for Embedded Systems. In: Proc. Int. Symp. Computer Architecture, pp. 136\u2013146 (2003)","DOI":"10.1145\/871656.859635"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures and Applications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11802839_31","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T09:05:46Z","timestamp":1736499946000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11802839_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540367086","9783540368632"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/11802839_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}