{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T20:33:14Z","timestamp":1743021194030,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":19,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540367086"},{"type":"electronic","value":"9783540368632"}],"license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11802839_36","type":"book-chapter","created":{"date-parts":[[2006,8,2]],"date-time":"2006-08-02T20:08:58Z","timestamp":1154549338000},"page":"274-286","source":"Crossref","is-referenced-by-count":2,"title":["PISC: Polymorphic Instruction Set Computers"],"prefix":"10.1007","author":[{"given":"Stamatis","family":"Vassiliadis","sequence":"first","affiliation":[]},{"given":"Georgi","family":"Kuzmanov","sequence":"additional","affiliation":[]},{"given":"Stephan","family":"Wong","sequence":"additional","affiliation":[]},{"given":"Elena","family":"Moscu-Panainte","sequence":"additional","affiliation":[]},{"given":"Georgi","family":"Gaydadjiev","sequence":"additional","affiliation":[]},{"given":"Koen","family":"Bertels","sequence":"additional","affiliation":[]},{"given":"Dmitry","family":"Cheresiz","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"2","key":"36_CR1","doi-asserted-by":"publisher","first-page":"59","DOI":"10.1147\/rd.381.0059","volume":"38","author":"S. Vassiliadis","year":"1994","unstructured":"Vassiliadis, S., Blaner, B., Eickemeyer, R.J.: SCISM: A scalable compound instruction set machine. IBM J. Res. Develop.\u00a038(2), 59\u201378 (1994)","journal-title":"IBM J. Res. Develop."},{"key":"36_CR2","doi-asserted-by":"crossref","unstructured":"Amdahl, G.M.: Validity of the single processor approach to achieving large scale computing capabilities. In: Proc. AFIPS 1967 Spring Joint Computer Conference, pp. 483\u2013485 (1967)","DOI":"10.1145\/1465482.1465560"},{"issue":"6","key":"36_CR3","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1145\/641914.641917","volume":"8","author":"D.A. Patterson","year":"1980","unstructured":"Patterson, D.A., Ditzel, D.R.: The case for the reduced instruction set computer. SIGARCH Comput. Archit. News\u00a08(6), 25\u201333 (1980)","journal-title":"SIGARCH Comput. Archit. News"},{"key":"36_CR4","doi-asserted-by":"crossref","unstructured":"Bhandarkar, D., Clark, D.W.: Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization. Communications of the ACM, 310\u2013319 (September 1991)","DOI":"10.1145\/106974.107003"},{"key":"36_CR5","unstructured":"Roelofs, G.: PNG: The Definitive Guide. O\u2019Reilly and Associates (1999)"},{"key":"36_CR6","doi-asserted-by":"crossref","unstructured":"Hakkennes, E.A., Vassiliadis, S.: Hardwired Paeth codec for portable network graphics (PNG). In: Proc. Euromicro 1999, pp. 318\u2013325 (1999)","DOI":"10.1109\/EURMIC.1999.794796"},{"key":"36_CR7","doi-asserted-by":"crossref","unstructured":"Hauck, S., Fry, T., Hosler, M., Kao, J.: The Chimaera Reconfigurable Functional Unit. In: Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 87\u201396 (1997)","DOI":"10.1109\/FPGA.1997.624608"},{"key":"36_CR8","unstructured":"Rosa, A.L., Lavagno, L., Passerone, C.: Hardware\/Software Design Space Exploration for a Reconfigurable Processor. In: Proc. Design, Automation and Test in Europe 2003 (DATE 2003), pp. 570\u2013575 (2003)"},{"issue":"4","key":"36_CR9","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1109\/MM.2003.1225960","volume":"23","author":"S. Vassiliadis","year":"2003","unstructured":"Vassiliadis, S., Wong, S., Cotofana, S.: Microcode Processing: Positioning and Directions. IEEE Micro\u00a023(4), 21\u201330 (2003)","journal-title":"IEEE Micro"},{"key":"36_CR10","doi-asserted-by":"crossref","unstructured":"Vassiliadis, S., Gaydadjiev, G., Bertels, K., Moscu Panainte, E.: The Molen Programming Paradigm. In: Proc. Third International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2003), pp. 1\u20137 (July 2003)","DOI":"10.1007\/978-3-540-27776-7_1"},{"key":"36_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"275","DOI":"10.1007\/3-540-44687-7_29","volume-title":"Field-Programmable Logic and Applications","author":"S. Vassiliadis","year":"2001","unstructured":"Vassiliadis, S., Wong, S., Cotofana, S.: The MOLEN \u03c1 \u03bc-Coded Processor. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol.\u00a02147, pp. 275\u2013285. Springer, Heidelberg (2001)"},{"key":"36_CR12","doi-asserted-by":"publisher","first-page":"1363","DOI":"10.1109\/TC.2004.104","volume":"53","author":"S. Vassiliadis","year":"2004","unstructured":"Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G., Panainte, E.M.: The Molen Polymorphic Processor. IEEE Transactions on Computers\u00a053, 1363\u20131375 (2004)","journal-title":"IEEE Transactions on Computers"},{"issue":"2","key":"36_CR13","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1109\/MDT.2003.1188264","volume":"20","author":"J.M.P. Cardoso","year":"2003","unstructured":"Cardoso, J.M.P., Neto, H.C.: Compilation for FPGA-Based Reconfigurable Hardware. IEEE Design & Test of Computers\u00a020(2), 65\u201375 (2003)","journal-title":"IEEE Design & Test of Computers"},{"key":"36_CR14","doi-asserted-by":"crossref","unstructured":"Kuzmanov, G., Gaydadjiev, G.N., Vassiliadis, S.: The MOLEN Processor Prototype. In: Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), pp. 296\u2013299 (April 2004)","DOI":"10.1109\/FCCM.2004.55"},{"key":"36_CR15","doi-asserted-by":"crossref","unstructured":"Moscu Panainte, E., Bertels, K., Vassiliadis, S.: Compiling for the Molen Programming Paradigm. In: Proc. 13th Int. Conf. on Field Programmable Logic and Applications (FPL), pp. 900\u2013910 (September 2003)","DOI":"10.1007\/978-3-540-45234-8_87"},{"key":"36_CR16","unstructured":"http:\/\/suif.stanford.edu\/suif\/suif2"},{"key":"36_CR17","unstructured":"http:\/\/www.eecs.hardvard.edu\/hube\/research\/machsuif.html"},{"key":"36_CR18","doi-asserted-by":"crossref","unstructured":"Gokhale, M., Stone, J.: Napa C: Compiling for a Hybrid RISC\/FPGA Architecture. In: Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 126\u2013135 (April 1998)","DOI":"10.1109\/FPGA.1998.707890"},{"key":"36_CR19","doi-asserted-by":"crossref","unstructured":"Moscu Panainte, E., Bertels, K., Vassiliadis, S.: Compiler-driven FPGA-area Allocation for Reconfigurable Computing. In: Proc. Design, Automation and Test in Europe 2006 (DATE 2006), pp. 369\u2013374 (March 2006)","DOI":"10.1109\/DATE.2006.243738"}],"container-title":["Lecture Notes in Computer Science","Reconfigurable Computing: Architectures and Applications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11802839_36","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T09:05:49Z","timestamp":1736499949000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11802839_36"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540367086","9783540368632"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/11802839_36","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}