{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T13:28:45Z","timestamp":1725542925064},"publisher-location":"Berlin, Heidelberg","reference-count":19,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540373766"},{"type":"electronic","value":"9783540373773"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11817949_31","type":"book-chapter","created":{"date-parts":[[2006,8,2]],"date-time":"2006-08-02T19:59:29Z","timestamp":1154548769000},"page":"465-476","source":"Crossref","is-referenced-by-count":23,"title":["On Interleaving in Timed Automata"],"prefix":"10.1007","author":[{"given":"Ramzi Ben","family":"Salah","sequence":"first","affiliation":[]},{"given":"Marius","family":"Bozga","sequence":"additional","affiliation":[]},{"given":"Oded","family":"Maler","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"31_CR1","doi-asserted-by":"publisher","first-page":"183","DOI":"10.1016\/0304-3975(94)90010-8","volume":"126","author":"R. Alur","year":"1994","unstructured":"Alur, R., Dill, D.L.: A Theory of Timed Automata. Theoretical Computer Science\u00a0126, 183\u2013235 (1994)","journal-title":"Theoretical Computer Science"},{"key":"31_CR2","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"485","DOI":"10.1007\/BFb0055643","volume-title":"CONCUR \u201998 Concurrency Theory","author":"J. Bengtsson","year":"1998","unstructured":"Bengtsson, J., Jonsson, B., Lilius, J., Yi, W.: Partial Order Reductions for Timed Systems. In: Sangiorgi, D., de Simone, R. (eds.) CONCUR 1998. LNCS, vol.\u00a01466, pp. 485\u2013500. Springer, Heidelberg (1998)"},{"key":"31_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"204","DOI":"10.1007\/978-3-540-40903-8_17","volume-title":"Formal Modeling and Analysis of Timed Systems","author":"R. Ben Salah","year":"2004","unstructured":"Ben Salah, R., Bozga, M., Maler, O.: On Timing Analysis of Combinational Circuits. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol.\u00a02791, pp. 204\u2013219. Springer, Heidelberg (2004)"},{"key":"31_CR4","unstructured":"Ben Salah, R., Bozga, M., Maler, O.: Automatic Abstraction of Timed Components (submitted, 2006)"},{"key":"31_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"343","DOI":"10.1007\/3-540-45657-0_26","volume-title":"Computer Aided Verification","author":"M. Bozga","year":"2002","unstructured":"Bozga, M., Graf, S., Mounier, L.: IF-2.0: A Validation Environment for Component-Based Real-Time Systems. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol.\u00a02404, pp. 343\u2013348. Springer, Heidelberg (2002)"},{"key":"31_CR6","doi-asserted-by":"publisher","first-page":"469","DOI":"10.1007\/s001650050028","volume":"10","author":"D. Dams","year":"1998","unstructured":"Dams, D., Gerth, R., Knaack, B., Kuiper, R.: Partial-order Reduction Techniques for Real-time Model Checking. Formal Aspects of Computing\u00a010, 469\u2013482 (1998)","journal-title":"Formal Aspects of Computing"},{"key":"31_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"313","DOI":"10.1007\/BFb0054180","volume-title":"Tools and Algorithms for the Construction and Analysis of Systems","author":"C. Daws","year":"1998","unstructured":"Daws, C., Tripakis, S.: Model Checking of Real-Time Reachability Properties Using Abstractions. In: Steffen, B. (ed.) TACAS 1998. LNCS, vol.\u00a01384, pp. 313\u2013329. Springer, Heidelberg (1998)"},{"key":"31_CR8","doi-asserted-by":"crossref","unstructured":"Daws, C., Yovine, S.: Reducing the Number of Clock Variables of Timed Automata. In: RTSS 1996, pp. 73\u201381 (1996)","DOI":"10.1109\/REAL.1996.563702"},{"key":"31_CR9","doi-asserted-by":"crossref","unstructured":"Diekert, V., Rozenberg, G. (eds.): The Book of Traces. World Scientific, Singapore (1995)","DOI":"10.1142\/2563"},{"key":"31_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1007\/978-3-540-40903-8_5","volume-title":"Formal Modeling and Analysis of Timed Systems","author":"M. Hendriks","year":"2004","unstructured":"Hendriks, M., Behrmann, G., Larsen, K., Niebert, P., Vaandrager, F.: Adding Symmetry Reduction to Uppaal. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol.\u00a02791, pp. 46\u201359. Springer, Heidelberg (2004)"},{"key":"31_CR11","doi-asserted-by":"crossref","unstructured":"Henzinger, T., Nicollin, X., Sifakis, J., Yovine, S.: Symbolic Model-checking for Real-time Systems. Information and Computation\u00a0111, 193\u2013244 (1994)","DOI":"10.1006\/inco.1994.1045"},{"key":"31_CR12","doi-asserted-by":"publisher","first-page":"27","DOI":"10.1016\/j.tcs.2005.07.023","volume":"345","author":"D. Lugiez","year":"2005","unstructured":"Lugiez, D., Niebert, P., Zennou, S.: A Partial Order Semantics Approach to the Clock Explosion Problem of Timed Automata. Theoretical Computer Science\u00a0345, 27\u201359 (2005)","journal-title":"Theoretical Computer Science"},{"key":"31_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"189","DOI":"10.1007\/3-540-60385-9_12","volume-title":"Correct Hardware Design and Verification Methods","author":"O. Maler","year":"1995","unstructured":"Maler, O., Pnueli, A.: Timing Analysis of Asynchronous Circuits using Timed Automata. In: Camurati, P.E., Eveking, H. (eds.) CHARME 1995. LNCS, vol.\u00a0987, pp. 189\u2013205. Springer, Heidelberg (1995)"},{"key":"31_CR14","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"431","DOI":"10.1007\/3-540-48320-9_30","volume-title":"CONCUR\u201999. Concurrency Theory","author":"M. Minea","year":"1999","unstructured":"Minea, M.: Partial Order Reduction for Model Checking of Timed Automata. In: Baeten, J.C.M., Mauw, S. (eds.) CONCUR 1999. LNCS, vol.\u00a01664, pp. 431\u2013446. Springer, Heidelberg (1999)"},{"key":"31_CR15","volume-title":"Representing and Modeling Digital Circuits","author":"T.G. Rokicki","year":"1994","unstructured":"Rokicki, T.G.: Representing and Modeling Digital Circuits. PhD Thesis, Stanford University (1994)"},{"key":"31_CR16","unstructured":"Tripakis, S.: The Analysis of Timed Systems in Practice, PhD Thesis, Universit\u00e9 Joseph Fourier, Grenoble (1998)"},{"key":"31_CR17","unstructured":"Uppaal benchmarks, www.it.uu.se\/research\/group\/darts\/uppaal\/benchmarks"},{"key":"31_CR18","doi-asserted-by":"crossref","unstructured":"Yoneda, T., Schlingloff, B.-H.: Efficient Verification of Parallel Real-Time Systems. Formal Methods in System Design,\u00a011, 187\u2013215 (1997)","DOI":"10.1023\/A:1008682131325"},{"key":"31_CR19","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"273","DOI":"10.1007\/978-3-540-40903-8_22","volume-title":"Formal Modeling and Analysis of Timed Systems","author":"S. Zennou","year":"2004","unstructured":"Zennou, S., Yguel, M., Niebert, P.: ELSE: A New Symbolic State Generator for Timed Automata. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol.\u00a02791, pp. 273\u2013280. Springer, Heidelberg (2004)"}],"container-title":["Lecture Notes in Computer Science","CONCUR 2006 \u2013 Concurrency Theory"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11817949_31.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T20:15:51Z","timestamp":1605644151000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11817949_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540373766","9783540373773"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/11817949_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}