{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,14]],"date-time":"2025-06-14T12:24:13Z","timestamp":1749903853745},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540374060"},{"type":"electronic","value":"9783540374114"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11817963_19","type":"book-chapter","created":{"date-parts":[[2006,8,5]],"date-time":"2006-08-05T05:07:51Z","timestamp":1154754471000},"page":"175-189","source":"Crossref","is-referenced-by-count":12,"title":["SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation"],"prefix":"10.1007","author":[{"given":"Jan-Willem","family":"Roorda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koen","family":"Claessen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"19_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"263","DOI":"10.1007\/3-540-40922-X_17","volume-title":"Formal Methods in Computer-Aided Design","author":"M. Aagaard","year":"2000","unstructured":"Aagaard, M., Jones, R.B., Melham, T.F., O\u2019Leary, J.W., Seger, C.-J.H.: A methodology for large-scale hardware verification. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol.\u00a01954, pp. 263\u2013282. Springer, Heidelberg (2000)"},{"key":"19_CR2","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"454","DOI":"10.1007\/3-540-44585-4_44","volume-title":"Computer Aided Verification","author":"P. Bjesse","year":"2001","unstructured":"Bjesse, P., Leonard, T., Mokkedem, A.: Finding bugs in an Alpha microprocessor using satisfiability solvers. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol.\u00a02102, p. 454. Springer, Heidelberg (2001)"},{"key":"19_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"502","DOI":"10.1007\/978-3-540-24605-3_37","volume-title":"Theory and Applications of Satisfiability Testing","author":"N. E\u00e9n","year":"2004","unstructured":"E\u00e9n, N., S\u00f6rensson, N.: An extensible SAT-solver. In: Giunchiglia, E., Tacchella, A. (eds.) SAT 2003. LNCS, vol.\u00a02919, pp. 502\u2013518. Springer, Heidelberg (2004)"},{"key":"19_CR4","unstructured":"FORTE, http:\/\/www.intel.com\/software\/products\/opensource\/tools1\/verification"},{"issue":"2","key":"19_CR5","doi-asserted-by":"publisher","first-page":"143","DOI":"10.1007\/s10009-004-0169-2","volume":"7","author":"B. Li","year":"2005","unstructured":"Li, B., Wang, C., Somenzi, F.: Abstraction refinement in symbolic model checking using satisfiability as the only decision procedure. Journal on STTT\u00a07(2), 143\u2013155 (2005)","journal-title":"Journal on STTT"},{"key":"19_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36126-X_1","volume-title":"Formal Methods in Computer-Aided Design","author":"T.F. Melham","year":"2002","unstructured":"Melham, T.F., Jones, R.B.: Abstraction by symbolic indexing transformations. In: Aagaard, M.D., O\u2019Leary, J.W. (eds.) FMCAD 2002. LNCS, vol.\u00a02517. Springer, Heidelberg (2002)"},{"key":"19_CR7","doi-asserted-by":"crossref","unstructured":"Pandey, M., Raimi, R., Bryant, R.E., Abadir, M.S.: Formal verification of content addressable memories using symbolic trajectory evaluation. In: DAC 1997 (1997)","DOI":"10.1145\/266021.266056"},{"key":"19_CR8","unstructured":"Roorda, J.-W.: Symbolic trajectory evaluation using a satisfiability solver. Licentiate thesis, Computing Science, Chalmers University of Technology (2005)"},{"key":"19_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"238","DOI":"10.1007\/11560548_19","volume-title":"Correct Hardware Design and Verification Methods","author":"J.-W. Roorda","year":"2005","unstructured":"Roorda, J.-W., Claessen, K.: A New SAT-Based Algorithm for Symbolic Trajectory Evaluation. In: Borrione, D., Paul, W. (eds.) CHARME 2005. LNCS, vol.\u00a03725, pp. 238\u2013253. Springer, Heidelberg (2005)"},{"key":"19_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"555","DOI":"10.1007\/11753728_56","volume-title":"Computer Science \u2013 Theory and Applications","author":"J.-W. Roorda","year":"2006","unstructured":"Roorda, J.-W., Claessen, K.: Explaining Symbolic Trajectory Evaluation by Giving it a Faithful Semantics. In: Grigoriev, D., Harrison, J., Hirsch, E.A. (eds.) CSR 2006. LNCS, vol.\u00a03967, pp. 555\u2013566. Springer, Heidelberg (2006)"},{"key":"19_CR11","first-page":"1","volume-title":"Proceedings of the 40th conference on Design automation","author":"T. Schubert","year":"2003","unstructured":"Schubert, T.: High level formal verification of next-generation microprocessors. In: Proceedings of the 40th conference on Design automation, pp. 1\u20136. ACM Press, New York (2003)"},{"key":"19_CR12","doi-asserted-by":"crossref","unstructured":"Seger, C.-J.H., Bryant, R.E.: Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design\u00a06(2) (1995)","DOI":"10.1007\/BF01383966"},{"key":"19_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1007\/11817963_20","volume-title":"Computer Aided Verification","author":"R. Tzoref","year":"2006","unstructured":"Tzoref, R., Grumberg, O.: Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, vol.\u00a04144, pp. 190\u2013204. Springer, Heidelberg (2006)"},{"key":"19_CR14","unstructured":"Yang, J., Gil, R., Singerman, E.: satGSTE: Combining the abstraction of GSTE with the capacity of a SAT solver. In: Designing Correct Circuits (DCC 2004) (2004)"}],"container-title":["Lecture Notes in Computer Science","Computer Aided Verification"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11817963_19.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T20:15:55Z","timestamp":1605644155000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11817963_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540374060","9783540374114"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/11817963_19","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}