{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:16:47Z","timestamp":1725470207236},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_17","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T13:54:06Z","timestamp":1157550846000},"page":"169-180","source":"Crossref","is-referenced-by-count":4,"title":["Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance"],"prefix":"10.1007","author":[{"given":"T.","family":"Murgan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P. B.","family":"Bacinschi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. Garc\u00eda","family":"Ortiz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Glesner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"9","key":"17_CR1","doi-asserted-by":"publisher","first-page":"969","DOI":"10.1109\/43.863637","volume":"19","author":"L. Benini","year":"2000","unstructured":"Benini, L., Macii, A., Macii, E., Poncino, M., Scarsi, R.: Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces. IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems\u00a019(9), 969\u2013980 (2000)","journal-title":"IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems"},{"issue":"1","key":"17_CR2","doi-asserted-by":"crossref","first-page":"23","DOI":"10.29292\/jics.v1i1.251","volume":"1","author":"A. Garc\u00eda Ortiz","year":"2004","unstructured":"Garc\u00eda Ortiz, A., Murgan, T., Kabulepa, L.D., Indrusiak, L.S., Glesner, M.: High-Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures. Journal of Integrated Circuits and Systems\u00a01(1), 23\u201331 (2004)","journal-title":"Journal of Integrated Circuits and Systems"},{"key":"17_CR3","unstructured":"International Technology Roadmap for Semiconductors, 2005 Edition. Interconnect (January 2006), http:\/\/www.itrs.net\/"},{"key":"17_CR4","doi-asserted-by":"crossref","unstructured":"Landman, P.E., Rabaey, J.M.: Power Estimation for High-level Synthesis. In: European Conf. on Design Automation with the European Event in ASIC Design, Paris, France, pp. 22\u201325 (February 1993)","DOI":"10.1109\/EDAC.1993.386449"},{"issue":"2","key":"17_CR5","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1109\/92.386219","volume":"3","author":"P.E. Landman","year":"1995","unstructured":"Landman, P.E., Rabaey, J.M.: Architectural Power Analysis: The Dual Bit Type Model. IEEE Trans. on Very Large Scale Integration (VLSI) Systems\u00a03(2), 173\u2013187 (1995)","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"key":"17_CR6","doi-asserted-by":"crossref","unstructured":"Lyuh, C.-G., Kim, T., Kim, K.-W.: Coupling-Aware High-level Interconnect Synthesis for Low Power. In: Intl. Conf. on Computer-Aided Design (ICCAD), San Jose, California, pp. 609\u2013613 (November 2002)","DOI":"10.1145\/774572.774662"},{"key":"17_CR7","unstructured":"Nanoscale Integration and Modeling (NIMO) Group, Arizona State Univ. Predictive Technology Model (December 2005), http:\/\/www.eas.asu.edu\/ptm\/"},{"issue":"2","key":"17_CR8","doi-asserted-by":"publisher","first-page":"212","DOI":"10.1109\/92.766748","volume":"7","author":"S. Ramprasad","year":"1999","unstructured":"Ramprasad, S., Shanbag, N.R., Hajj, I.N.: A Coding Framework for Low-Power Address and Data Busses. IEEE Trans. on Very Large Scale Integration (VLSI) Systems\u00a07(2), 212\u2013221 (1999)","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"issue":"7","key":"17_CR9","doi-asserted-by":"publisher","first-page":"718","DOI":"10.1109\/43.644033","volume":"16","author":"S. Ramprasad","year":"1997","unstructured":"Ramprasad, S., Shanbhag, N.R., Hajj, I.N.: Analytical Estimation of Signal Transition Activity from Word-Level Statistics. IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems\u00a016(7), 718\u2013733 (1997)","journal-title":"IEEE Trans. on Computer-Aided Design (CAD) of Integrated Circuits and Systems"},{"key":"17_CR10","doi-asserted-by":"crossref","unstructured":"Shin, Y., Chae, S.-I., Choi, K.: Partial Bus-Invert Coding for Power Optimization of Application-Specific Systems \u00a09(2), 377\u2013383 (2001)","DOI":"10.1109\/92.924059"},{"key":"17_CR11","doi-asserted-by":"crossref","unstructured":"Sotiriadis, P.P., Chandrakasan, A.P.: Low Power Coding Techniques Considering Inter-Wire Capacitance. In: Custom Integrated Circuits Conf., Orlando, Florida, pp. 507\u2013510 (May 2000)","DOI":"10.1109\/CICC.2000.852719"},{"issue":"1","key":"17_CR12","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1109\/92.365453","volume":"3","author":"M.R. Stan","year":"1995","unstructured":"Stan, M.R., Burleson, W.P.: Bus-Invert Coding for Low-Power I\/O. IEEE Trans. on Very Large Scale Integration (VLSI) Systems\u00a03(1), 49\u201358 (1995)","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"issue":"4","key":"17_CR13","doi-asserted-by":"publisher","first-page":"444","DOI":"10.1109\/92.645071","volume":"5","author":"M.R. Stan","year":"1997","unstructured":"Stan, M.R., Burleson, W.P.: Low-Power Encodings for Global Communication in CMOS VLSI. IEEE Trans. on Very Large Scale Integration (VLSI) Systems\u00a05(4), 444\u2013455 (1997)","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"key":"17_CR14","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Lach, J., Skadron, K., Stan, M.R.: Odd\/Even Bus Invert with Two-Phase Transfer for Buses with Coupling. In: Intl. Symp. on Low Power Electronics and Design (ISLPED), Monterey, California, pp. 80\u201383 (August 2002)","DOI":"10.1145\/566408.566431"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11847083_17.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T03:47:12Z","timestamp":1627789632000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11847083_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/11847083_17","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}