{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T20:10:30Z","timestamp":1736539830152,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":27,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_19","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T13:54:06Z","timestamp":1157550846000},"page":"191-202","source":"Crossref","is-referenced-by-count":5,"title":["Two Efficient Synchronous $\\Leftrightarrow$ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures"],"prefix":"10.1007","author":[{"given":"A.","family":"Sheibanyrad","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Greiner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"19_CR1","doi-asserted-by":"crossref","unstructured":"Nilsson, E., \u00d6berg, J.: Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking. In: 2nd IEEE\/ACM\/IFIP international Conference on Hardware\/Software Codesign and System Synthesis, Stockholm, Sweden, September 8 - 10 (2004)","DOI":"10.1145\/1016720.1016764"},{"key":"19_CR2","doi-asserted-by":"crossref","unstructured":"Dennison, L.R., Dally, W.J., Xanthopoulos, D.: Low-latency plesiochronous data retiming. In: 16th Conference on Advanced Research in VLSI (ARVLSI 1995), p. 304 (1995)","DOI":"10.1109\/ARVLSI.1995.515628"},{"issue":"1","key":"19_CR3","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1109\/12.75145","volume":"37","author":"W.K. Stewart","year":"1988","unstructured":"Stewart, W.K., Ward, S.A.: A Solution to a Special Case of the Synchronization Problem. IEEE Transactions on Computers\u00a037(1), 123\u2013125 (1988)","journal-title":"IEEE Transactions on Computers"},{"key":"19_CR4","doi-asserted-by":"crossref","unstructured":"Chakraborty, A., Greenstreet, M.R.: Efficient Self-Timed Interfaces for Crossing Clock Domains. In: 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2003), p. 78 (2003)","DOI":"10.1109\/ASYNC.2003.1199168"},{"key":"19_CR5","doi-asserted-by":"crossref","unstructured":"Semiat, Y., Ginosar, R.: Timing Measurements of Synchronization Circuits. In: 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2003), p. 68 (2003)","DOI":"10.1109\/ASYNC.2003.1199167"},{"key":"19_CR6","doi-asserted-by":"crossref","unstructured":"Ginosar, R., Kol, R.: Adaptive Synchronization. In: IEEE International Conference on Computer Design (ICCD 1998), p. 188 (1998)","DOI":"10.1109\/ICCD.1998.727042"},{"key":"19_CR7","doi-asserted-by":"crossref","unstructured":"Mekie, J., Chakraborty, S., Sharma, D.K., Venkataramani, G., Thiagarajan, P.S.: Interface Design for Rationally Clocked GALS Systems. In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), pp. 160\u2013171 (2006)","DOI":"10.1109\/ASYNC.2006.19"},{"key":"19_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"402","DOI":"10.1007\/978-3-540-30205-6_42","volume-title":"Integrated Circuit and System Design","author":"U. Frank","year":"2004","unstructured":"Frank, U., Ginosar, R.: A Predictive Synchronizer for Periodic Clock Domains. In: Macii, E., Paliouras, V., Koufopavlou, O. (eds.) PATMOS 2004. LNCS, vol.\u00a03254, pp. 402\u2013412. Springer, Heidelberg (2004)"},{"key":"19_CR9","doi-asserted-by":"crossref","unstructured":"Sarmenta, L.F.G., Pratt, G.A., Ward, S.A.: Rational clocking [digital systems design]. In: IEEE International Conference on Computer Design (ICCD 1995), p. 271 (1995)","DOI":"10.1109\/ICCD.1995.528821"},{"key":"19_CR10","doi-asserted-by":"crossref","unstructured":"Nowick, S.M., Chelcea, T.: Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. In: 38th Conference on Design Automation (DAC 2001), pp. 21\u201326 (2001)","DOI":"10.1145\/378239.378256"},{"key":"19_CR11","first-page":"598","volume":"5","author":"J. Jex","year":"1997","unstructured":"Jex, J., Dike, C., Self, K.: Fully asynchronous interface with programmable metastability settling time synchronizer, US Patent 5 598 113 (1997)","journal-title":"US Patent"},{"key":"19_CR12","doi-asserted-by":"crossref","unstructured":"Yun, K.Y., Donohue, R.P.: Pausible Clocking: A First Step Toward Heterogeneous Systems. In: IEEE International Conference on Computer Design (ICCD 1996), p. 118 (1996)","DOI":"10.1109\/ICCD.1996.563543"},{"key":"19_CR13","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-3385-3","volume-title":"Principles of Asynchronous Circuit Design \u2013 A Systems Perspective","author":"J. Sparsoe","year":"2001","unstructured":"Sparsoe, J., Furber, S.: Principles of Asynchronous Circuit Design \u2013 A Systems Perspective. Kluwer Academic Publishers, Dordrecht (2001)"},{"key":"19_CR14","doi-asserted-by":"crossref","unstructured":"Seizovic, J.N.: Pipeline synchronization. In: International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 87\u201396 (November 1994)","DOI":"10.1109\/ASYNC.1994.656289"},{"key":"19_CR15","doi-asserted-by":"crossref","unstructured":"Moore, S., Taylor, G., Robinson, P., Mullins, R.: Point to Point GALS Interconnect. In: 8th International Symposium on Asynchronous Circuits and Systems (ASYNC 2002), p. 69 (2002)","DOI":"10.1109\/ASYNC.2002.1000297"},{"key":"19_CR16","doi-asserted-by":"crossref","unstructured":"Bormann, D.S., Cheung, P.Y.K.: Asynchronous Wrapper for Heterogeneous Systems. In: IEEE International Conference on Computer Design (ICCD 1997), p. 307 (1997)","DOI":"10.1109\/ICCD.1997.628884"},{"key":"19_CR17","doi-asserted-by":"crossref","unstructured":"Sjogren, A.E., Myers, C.J.: Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. In: 17th Conference on Advanced Research in VLSI (ARVLSI 1997), p. 47 (1997)","DOI":"10.1109\/ARVLSI.1997.634845"},{"key":"19_CR18","doi-asserted-by":"crossref","unstructured":"Dobkin (Reuven), R., Ginosar, R., Sotiriou, C.P.: Data Synchronization Issues in GALS SoCs. In: 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2004), pp. 170\u2013180 (2004)","DOI":"10.1109\/ASYNC.2004.1299298"},{"key":"19_CR19","unstructured":"Ghahremani, S.: Metastable Protected Latch, US Patent 6 072346 (2000)"},{"key":"19_CR20","unstructured":"Greiner, A., P\u00eacheux, F.: ALLIANCE. A Complete Set of CAD Tools for Teaching VLSI Design. In: 3rd Eurochip Workshop on VLSI Design Training, Grenoble, France, pp. 230\u2013237 (1992)"},{"key":"19_CR21","doi-asserted-by":"crossref","unstructured":"Ginosar, R.: Fourteen Ways to Fool Your Synchronizer. In: 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2003), p. 89 (2003)","DOI":"10.1109\/ASYNC.2003.1199169"},{"issue":"6","key":"19_CR22","doi-asserted-by":"publisher","first-page":"849","DOI":"10.1109\/4.766819","volume":"34","author":"C. Dike","year":"1999","unstructured":"Dike, C., Burton, e.: Miller and Noise Effects in A synchronizing flip-flop. IEEE J. Solid-state circuits\u00a034(6), 849\u2013855 (1999)","journal-title":"IEEE J. Solid-state circuits"},{"issue":"2","key":"19_CR23","doi-asserted-by":"publisher","first-page":"202","DOI":"10.1109\/4.982426","volume":"37","author":"D.J. Kinniment","year":"2002","unstructured":"Kinniment, D.J., Bystrov, A., Yakovlev, A.V.: Synchronization Circuit Performance. IEEE Journal of Solid-State Circuits\u00a037(2), 202\u2013209 (2002)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"19_CR24","unstructured":"http:\/\/www-asim.lip6.fr\/recherche\/alliance\/"},{"key":"19_CR25","unstructured":"http:\/\/www-asim.lip6.fr\/recherche\/coriolis\/"},{"key":"19_CR26","volume-title":"Proceedings of the Design, Automation and Test in Europe Conference","author":"T. Bjerregaard","year":"2005","unstructured":"Bjerregaard, T., Spars\u00f8, J.: A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. In: Proceedings of the Design, Automation and Test in Europe Conference. IEEE, Los Alamitos (2005)"},{"key":"19_CR27","volume-title":"Proceedings of the International Symposium on System-on-Chip","author":"T. Bjerregaard","year":"2005","unstructured":"Bjerregaard, T., Mahadevan, S., Olsen, R., Spars\u00f8, J.: An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip. In: Proceedings of the International Symposium on System-on-Chip. IEEE, Los Alamitos (2005)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11847083_19.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:39:40Z","timestamp":1736537980000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11847083_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":27,"URL":"https:\/\/doi.org\/10.1007\/11847083_19","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}