{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T20:10:04Z","timestamp":1736539804352,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_29","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T13:54:06Z","timestamp":1157550846000},"page":"301-310","source":"Crossref","is-referenced-by-count":2,"title":["Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis"],"prefix":"10.1007","author":[{"given":"Daniel Lima","family":"Ferr\u00e3o","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ricardo","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 Lu\u00eds","family":"G\u00fcntzel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"29_CR1","doi-asserted-by":"crossref","unstructured":"Chen, H.-C., Du, D.: Path Sensitization in Critical Path Problem. IEEE Transactions on CAD of Integrated Circuits and Systems\u00a012(2), 196\u2013207","DOI":"10.1109\/43.205001"},{"key":"29_CR2","doi-asserted-by":"crossref","unstructured":"Devadas, S., Keutzer, K., Malik, S.: Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms. IEEE Transactions on Computed-Aided Design of Integrated Circuits and Systems\u00a012(12), 1913\u20131923","DOI":"10.1109\/43.251155"},{"key":"29_CR3","doi-asserted-by":"crossref","unstructured":"Chang, H., Abraham, J.A.: VIPER: An Efficient Vigorously Sensitizable Path Extractor. In: 30th ACM\/IEEE Design Automation Conference, pp. 112\u2013117 (1993)","DOI":"10.1145\/157485.158845"},{"key":"29_CR4","doi-asserted-by":"crossref","unstructured":"Devadas, S., Keutzer, K., Malik, S., Wang, A.: Computation of Floating Mode Delay in Combinational Circuits: Practice and Implementation. IEEE Transactions on Computed-Aided Design of Integrated Circuits and Systems\u00a012(12), 1924\u20131936","DOI":"10.1109\/43.251156"},{"key":"29_CR5","doi-asserted-by":"crossref","unstructured":"Silva, L.G., et al.: Realistic Delay Modeling in Satisfiability-Based Timing Analysis. In: IEEE Intl. Symposium on Circuits & Systems (ISCAS), vol.\u00a06, pp. 215\u2013218 (1998)","DOI":"10.1109\/ISCAS.1998.705250"},{"key":"29_CR6","doi-asserted-by":"crossref","first-page":"167","DOI":"10.1007\/978-1-4615-3154-8_8","volume-title":"Logic Synthesis and Optimization","author":"P. McGeer","year":"1993","unstructured":"McGeer, P., et al.: Delay Models and Exact Timing Analysis. In: Sasao, T. (ed.) Logic Synthesis and Optimization, pp. 167\u2013189. Kluwer Academic Pub., Dordrecht (1993)"},{"key":"29_CR7","doi-asserted-by":"crossref","unstructured":"Goel, P.: An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers\u00a0C-30(3), 215\u2013222","DOI":"10.1109\/TC.1981.1675757"},{"key":"29_CR8","doi-asserted-by":"crossref","unstructured":"Fujiwara, H., Shimono, T.: On the Acceleration of Test Generation Algorithms. IEEE Transactions on Computers\u00a0C-32(12), 1137\u20131144","DOI":"10.1109\/TC.1983.1676174"},{"key":"29_CR9","doi-asserted-by":"crossref","unstructured":"Blaqui\u00e8re, Y., Dagenais, M., Savaria, Y.: Timing Analysis Speed-up Using a Hierarchical and a Multimode Approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a015(2), 244\u2013255","DOI":"10.1109\/43.486669"},{"key":"29_CR10","unstructured":"Heo, S., Kim, J.: Hierarchical Timing Analysis Considering Global False Path. In: Proceedings of ITC-CSCC-2002 (2002)"},{"key":"29_CR11","doi-asserted-by":"crossref","unstructured":"Kukimoto, Y., Brayton, R.K.: Hierarchical Functional Timing Analysis. In: 35th ACM\/IEEE Design Automation Conference, pp. 580\u2013585 (1998)","DOI":"10.1145\/277044.277197"},{"key":"29_CR12","unstructured":"Cadence Physically Knowledgeable Synthesis\u00ae User Guide. Cadence Design Systems, Inc. (2002)"},{"key":"29_CR13","unstructured":"Synopsys PrimeTime\u00ae User Guide: Advanced Timing Analysis. Synopsys, Inc. (2004)"},{"key":"29_CR14","doi-asserted-by":"crossref","unstructured":"Yalcin, H., Hayes, J.P.: Hierarchical Timing Analysis Using Conditional Delays. In: Proceedings of International Conference on Computer Aided Design, pp. 371\u2013377 (1995)","DOI":"10.1109\/ICCAD.1995.480143"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11847083_29","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:39:35Z","timestamp":1736537975000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11847083_29"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/11847083_29","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}