{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:16:53Z","timestamp":1725470213956},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_39","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T13:54:06Z","timestamp":1157550846000},"page":"403-414","source":"Crossref","is-referenced-by-count":0,"title":["Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources"],"prefix":"10.1007","author":[{"given":"Kostas","family":"Siozios","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitrios","family":"Soudris","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonios","family":"Thanailakis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"39_CR1","volume-title":"Low-Energy FPGAs- Architecture and Design","author":"G. Varghese","year":"2001","unstructured":"Varghese, G., Rabaey, J.M.: Low-Energy FPGAs- Architecture and Design. Kluwer Academic Publishers, Dordrecht (2001)"},{"key":"39_CR2","doi-asserted-by":"crossref","unstructured":"Siozios, K., et al.: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. In: 15th Int. Conf. FPL 2005, pp. 658\u2013661 (August 26-28, 2005)","DOI":"10.1109\/FPL.2005.1515807"},{"key":"39_CR3","unstructured":"Yang, S.: Logic Synthesis and Optimization Benchmarks, Version 3.0, Tech.Report, Microelectronics Centre of North Carolina (1991)"},{"key":"39_CR4","doi-asserted-by":"crossref","unstructured":"Leijten-Nowak, K., van Meerbergen, J.L.: An FPGA Architecture with Enhanced Datapath Functionality. In: FPGA 2003, California, USA, pp. 195\u2013204 (February 2003)","DOI":"10.1145\/611817.611846"},{"key":"39_CR5","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5145-4","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"V. Betz","year":"1999","unstructured":"Betz, V., Rose, J., Marquardt, A.: Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Dordrecht (1999)"},{"key":"39_CR6","unstructured":"http:\/\/vlsi.ee.duth.gr\/amdrel"},{"key":"39_CR7","unstructured":"http:\/\/www.xilinx.com\/products\/silicon-solutions\/fpgas\/virtex\/virtex4\/overview"},{"key":"39_CR8","unstructured":"Deliverable Report D9: Survey of existing fine-grain reconfigurable hardware platforms, AMDREL project, Available at: http:\/\/vlsi.ee.duth.gr\/amdrel\/pdf\/d9_final.pdf"},{"key":"39_CR9","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-4941-0","volume-title":"Design of Interconnection Networks for Programmable Logic","author":"G. Lemieux","year":"2004","unstructured":"Lemieux, G., Lewis, D.: Design of Interconnection Networks for Programmable Logic. Kluwer Academic Publishers, Dordrecht (2004)"},{"key":"39_CR10","doi-asserted-by":"crossref","unstructured":"Poon, K., Yan, A., Wilton, S.: A Flexible Power Model for FPGAs. In: Proc. of 15th Int. Conf. on Field Programmable Logic and Applications, pp. 312\u2013321 (2002)","DOI":"10.1007\/3-540-46117-5_33"},{"key":"39_CR11","doi-asserted-by":"crossref","unstructured":"Cheng, L., Wong, P., Li, F., Lin, Y., He, L.: Device and Architecture Co-Optimization for FPGA Power Reduction. In: Proc. of Design Automation Conference, pp. 915\u2013920 (June 13-17, 2005)","DOI":"10.1145\/1065579.1065819"},{"key":"39_CR12","doi-asserted-by":"crossref","unstructured":"Dehon, A.: Balancing interconnect and computation in a reconfigurable computing array (or, why you don\u2019t really want 100% LUT utilization). In: Proc. of Int. Symp. on Field Programmable Gate Arrays, pp. 69\u201378 (1999)","DOI":"10.1145\/296399.296431"},{"key":"39_CR13","doi-asserted-by":"crossref","unstructured":"Siozios, K., et al.: A Novel Methodology for Designing High-Performance and Low-Power FPGA Interconnection Targeting DSP Applications. In: Proc. of IEEE Int. Symp. on Circuits and Systems, May 21-24 (2006)","DOI":"10.1109\/ISCAS.2006.1693600"},{"key":"39_CR14","doi-asserted-by":"crossref","unstructured":"Ebeling, C., McMurchie, L., Hauck, S.A., Burns, S.: Placement and Routing Tools for the Triptych FPGA. IEEE Trans. on VLSI, 473\u2013482 (December 1995)","DOI":"10.1109\/92.475966"},{"key":"39_CR15","unstructured":"Siozios, K., Tatas, K., Soudris, D., Thanailakis, A.: Platform-based FPGA Architecture: Designing High-Performance and Low-Power Routing Structure for Realizing DSP Applications. In: RAW 2006, 13th Reconfigurable Architectures Workshop, Rhodes, Greece, April 25-26, 2006 (accepted for presentation, 2006)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11847083_39.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T19:42:00Z","timestamp":1605642120000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11847083_39"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/11847083_39","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}