{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,17]],"date-time":"2025-10-17T13:28:31Z","timestamp":1760707711575},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_40","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T13:54:06Z","timestamp":1157550846000},"page":"415-424","source":"Crossref","is-referenced-by-count":10,"title":["An FPGA Power Aware Design Flow"],"prefix":"10.1007","author":[{"given":"David","family":"Ell\u00e9ouet","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yannig","family":"Savary","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nathalie","family":"Julien","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"40_CR1","doi-asserted-by":"crossref","unstructured":"Anderson, J.H., Najm, F.N., Tuan, T., et al.: Active leakage power optimization for fpgas. In: FPGA 2004, vol.\u00a028, pp. 33\u201341 (2004)","DOI":"10.1145\/968280.968287"},{"key":"40_CR2","doi-asserted-by":"crossref","unstructured":"Chen, D., Cong, J., Fan, Y., et al.: Low-power high-level synthesis for fpga architectures. In: ISPLED 2003 (2003)","DOI":"10.1145\/871540.871541"},{"key":"40_CR3","doi-asserted-by":"crossref","unstructured":"Chen, D., Cong, J., Li, F., He, L., et al.: Low-power technology mapping for fpga architectures with dual supply voltages. In: FPGA 2004 (2004)","DOI":"10.1145\/968280.968297"},{"key":"40_CR4","doi-asserted-by":"crossref","unstructured":"Ell\u00e9ouet, D., Julien, N., Houzet, D., Cousin, J.G., Martin, E., et al.: Power consumption characterization and modeling of embedded memories in xilinx virtex 400e fpga. In: EUROMICRO Symposium on Digital System Design (2004)","DOI":"10.1109\/DSD.2004.1333302"},{"key":"40_CR5","doi-asserted-by":"crossref","unstructured":"Gayasen, A., Tsai, Y., Kandemir, M., Irwin, M.J., Tuan, T., et al.: Reducing leakage energy in fpgas using region-constrained placement. In: FPGA 2004, pp. 51\u201358 (2004)","DOI":"10.1145\/968280.968289"},{"key":"40_CR6","volume-title":"Power\/energy estimation in socs by multi-level parametric modeling","author":"N. Julien","year":"2005","unstructured":"Julien, N., Laurent, J., Senn, E., Elleouet, D., Savary, Y., Abdelli, N., Ktari, J., et al.: Power\/energy estimation in socs by multi-level parametric modeling. Kluwer Academic Publisher, Dordrecht (2005)"},{"issue":"5","key":"40_CR7","doi-asserted-by":"publisher","first-page":"40","DOI":"10.1109\/MM.2003.1240211","volume":"23","author":"N. Julien","year":"2003","unstructured":"Julien, N., Laurent, J., Senn, E., Martin, E., et al.: Power consumption modeling and characterization of the TI C6201. IEEE Micro\u00a023(5), 40\u201349 (2003)","journal-title":"IEEE Micro"},{"key":"40_CR8","unstructured":"Laurent, J., Julien, N., Senn, E., Martin, E., et al.: Functionnal level power analysis: An efficient approach for modeling the power consumption of complex processors. In: IEEE DATE, vol.\u00a023 (2004)"},{"key":"40_CR9","doi-asserted-by":"crossref","unstructured":"Li, F., Chen, D., He, L., Cong, J., et al.: Architecture evaluation for power-efficient fpgas. In: FPGA 2003 (2003)","DOI":"10.1145\/611843.611844"},{"key":"40_CR10","unstructured":"Martin, E., Stentieys, O., Dubois, H., Philippe, J.L., et al.: Gaut: An architectural synthesis tool for dedicated signal processors. In: EURO-DAC 1993, Hambourg, Germany, September 20-24 (1993)"},{"key":"40_CR11","doi-asserted-by":"publisher","first-page":"456","DOI":"10.1109\/TASSP.1974.1162619","volume":"ASSP-22","author":"Peled","year":"1974","unstructured":"Peled, Liu, B., et al.: A new hardware realization of digital filters. IIEEE Trans. on Acoust., Speech, Signal Processing\u00a0ASSP-22, 456\u2013462 (1974)","journal-title":"IIEEE Trans. on Acoust., Speech, Signal Processing"},{"key":"40_CR12","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-2307-9","volume-title":"Low power design methodologies","author":"J.M. Rabaey","year":"1996","unstructured":"Rabaey, J.M., Pedram, M., et al.: Low power design methodologies. Kluwer Academic Publisher, Dordrecht (1996)"},{"key":"40_CR13","doi-asserted-by":"crossref","unstructured":"Shang, L., Kaviani, A.S., Bathala, K., et al.: Dynamic power consumption in virtex-ii fpga family. In: FPGA 2002 (2002)","DOI":"10.1145\/503048.503072"},{"key":"40_CR14","unstructured":"Sung, N.S., Austin, T., Blaauw, D., Mudge, T., Flautner, K., Hu, J.S., Irwin, M.J., Kandemir, M., Narayanan, V., et al.: Leakage current: Moore\u2019s law meets static power. IEEE Computer Magazine (2003)"},{"key":"40_CR15","volume-title":"Low energy FPGAs - architecture and design","author":"G. Varghese","year":"2001","unstructured":"Varghese, G., Rabaey, J.M., et al.: Low energy FPGAs - architecture and design. Kluwer Academic Publisher, Dordrecht (2001)"},{"issue":"3","key":"40_CR16","doi-asserted-by":"publisher","first-page":"4","DOI":"10.1109\/53.29648","volume":"6","author":"S.A. White","year":"1989","unstructured":"White, S.A.: Applications of distributed arithmetic to digital signal processing. IEEE ASSP Magazine\u00a06(3), 4\u201319 (1989)","journal-title":"IEEE ASSP Magazine"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11847083_40","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,19]],"date-time":"2019-05-19T17:13:57Z","timestamp":1558286037000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11847083_40"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/11847083_40","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}