{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:17:01Z","timestamp":1725470221684},"publisher-location":"Berlin, Heidelberg","reference-count":5,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_43","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T09:54:06Z","timestamp":1157536446000},"page":"450-457","source":"Crossref","is-referenced-by-count":0,"title":["Hierarchical Modeling of a Fractional Phase Locked Loop"],"prefix":"10.1007","author":[{"given":"Benjamin","family":"Nicolle","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"William","family":"Tatinian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean","family":"Oudinot","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gilles","family":"Jacquemod","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"43_CR1","doi-asserted-by":"crossref","unstructured":"Nicolle, B., et al.: VHDL-AMS modeling of a multistandard Phase Locked Loop. In: ICECS 2005 Proceeding, pp. 33\u201336 (2005)","DOI":"10.1109\/ICECS.2005.4633374"},{"issue":"1","key":"43_CR2","doi-asserted-by":"publisher","first-page":"4962","DOI":"10.1109\/JSSC.2003.820858","volume":"39","author":"Pamarti","year":"2004","unstructured":"Pamarti, Jansson, Galton: A Wideband 2.4GHz Delta Sigma Fractional N PLL with 1Mb\/s in loop modulation. IEEE Journal of Solid State Circuits\u00a039(1), 4962 (2004)","journal-title":"IEEE Journal of Solid State Circuits"},{"key":"43_CR3","unstructured":"Application notes for ADS Software, PLL Transient Response Simulation, Tutorial"},{"key":"43_CR4","unstructured":"Allen, P.E.: CMOS phase locked loops Lecture 130 (2003)"},{"key":"43_CR5","doi-asserted-by":"crossref","unstructured":"Juarez-Hernandez, E., Diaz-Sanchez, A.: A novel CMOS charge-pump circuit with positive feedback for PLL applications. In: Electro 2001 (2001)","DOI":"10.1109\/ICECS.2001.957751"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11847083_43.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T14:42:00Z","timestamp":1605624120000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11847083_43"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":5,"URL":"https:\/\/doi.org\/10.1007\/11847083_43","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}