{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T20:10:08Z","timestamp":1736539808004,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540390947"},{"type":"electronic","value":"9783540390978"}],"license":[{"start":{"date-parts":[[2006,1,1]],"date-time":"2006-01-01T00:00:00Z","timestamp":1136073600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11847083_49","type":"book-chapter","created":{"date-parts":[[2006,9,6]],"date-time":"2006-09-06T13:54:06Z","timestamp":1157550846000},"page":"504-513","source":"Crossref","is-referenced-by-count":0,"title":["Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling"],"prefix":"10.1007","author":[{"given":"Saihua","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"49_CR1","doi-asserted-by":"publisher","first-page":"1836","DOI":"10.1109\/22.641781","volume":"45","author":"A. Deutsch","year":"1997","unstructured":"Deutsch, A., et al.: When are Transmission Line Effects Important for On-Chip Interconnections? IEEE Transactions on Microwave Theory and Techniques\u00a045, 1836\u20131846 (1997)","journal-title":"IEEE Transactions on Microwave Theory and Techniques"},{"unstructured":"Sun, J., Zheng, Y., Ye, Q., Ye, T.: Worst-case crosstalk noise analysis based on dual-exponential noise metrics. In: Proc. VLSID 2005, pp. 348\u2013353 (2005)","key":"49_CR2"},{"issue":"5","key":"49_CR3","doi-asserted-by":"publisher","first-page":"627","DOI":"10.1109\/TCAD.2003.810741","volume":"22","author":"L. Ding","year":"2003","unstructured":"Ding, L., Blaauw, D., Mazumder, P.: Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. Computed-Aided Design of Integr. Circuits Syst.\u00a022(5), 627\u2013634 (2003)","journal-title":"IEEE Trans. Computed-Aided Design of Integr. Circuits Syst."},{"issue":"3","key":"49_CR4","doi-asserted-by":"publisher","first-page":"290","DOI":"10.1109\/43.594834","volume":"16","author":"A. Vittal","year":"1997","unstructured":"Vittal, A., Marek-Sadowska, M.: Crosstalk reduction for VLSI. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst.\u00a016(3), 290\u2013298 (1997)","journal-title":"IEEE Trans. Computer-Aided Design of Integr. Circuits Syst."},{"issue":"12","key":"49_CR5","doi-asserted-by":"publisher","first-page":"1817","DOI":"10.1109\/43.811330","volume":"18","author":"A. Vittal","year":"1999","unstructured":"Vittal, A., Chen, L.H., Marek-Sadowska, M., Wang, K.-P., Yang, S.: Crosstalk in VLSI interconnections. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst.\u00a018(12), 1817\u20131824 (1999)","journal-title":"IEEE Trans. Computer-Aided Design of Integr. Circuits Syst."},{"doi-asserted-by":"crossref","unstructured":"Palit, A.K., Meyer, V., Anheier, W., Schloeffel, J.: ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips. In: Proc. VLSID 2005, pp. 354\u2013359 (2005)","key":"49_CR6","DOI":"10.1109\/ICVD.2005.40"},{"issue":"11","key":"49_CR7","doi-asserted-by":"publisher","first-page":"2078","DOI":"10.1109\/16.877169","volume":"47","author":"J. Davis","year":"2005","unstructured":"Davis, J., Meindl, J.: Compact Distributed RLC Interconnect Models \u2013 Part II: Coupled Line Transient Expressions and Peak Crosstalk in Multilevel Networks. IEEE Trans. Electron Devices\u00a047(11), 2078\u20132087 (2005)","journal-title":"IEEE Trans. Electron Devices"},{"issue":"8","key":"49_CR8","doi-asserted-by":"publisher","first-page":"904","DOI":"10.1109\/TCAD.2002.800459","volume":"21","author":"K. Banerjee","year":"2002","unstructured":"Banerjee, K., Mehrotra, A.: Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst.\u00a021(8), 904\u2013915 (2002)","journal-title":"IEEE Trans. Computer-Aided Design of Integr. Circuits Syst."},{"doi-asserted-by":"crossref","unstructured":"Lin, S., Yang, H.: A novel \u03b3d\/n RLCG transmission line model considering complex RC(L) loads. IEEE Trans. Computer-Aided Design of Integr. Circuits Syst. (submitted, 2006)","key":"49_CR9","DOI":"10.1109\/TCAD.2006.884413"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11847083_49","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T19:39:45Z","timestamp":1736537985000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11847083_49"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540390947","9783540390978"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/11847083_49","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}