{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T22:40:19Z","timestamp":1736635219930,"version":"3.32.0"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540446248"},{"type":"electronic","value":"9783540446279"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11864219_12","type":"book-chapter","created":{"date-parts":[[2006,10,4]],"date-time":"2006-10-04T05:25:39Z","timestamp":1159939539000},"page":"164-178","source":"Crossref","is-referenced-by-count":0,"title":["Capturing Register and Control Dependence in Memory Consistency Models with Applications to the Itanium Architecture"],"prefix":"10.1007","author":[{"given":"Lisa","family":"Higham","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"LillAnne","family":"Jackson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jalal","family":"Kawash","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"5","key":"12_CR1","doi-asserted-by":"publisher","first-page":"502","DOI":"10.1109\/TPDS.2003.1199067","volume":"14","author":"A. Adir","year":"2003","unstructured":"Adir, A., Attiya, H., Shurek, G.: Information-flow models for shared memory with an application to the PowerPC architecture. IEEE Trans. on Parallel and Distributed Systems\u00a014(5), 502\u2013515 (2003)","journal-title":"IEEE Trans. on Parallel and Distributed Systems"},{"key":"12_CR2","doi-asserted-by":"crossref","unstructured":"Attiya, H., Friedman, R.: Programming DEC-Alpha based multiprocessors the easy way. In: Proc. 6th Int\u2019l Symp. on Parallel Algorithms and Architectures, pp. 157\u2013166 (1994), Technical Report LPCR 9411, Computer Science Department, Technion","DOI":"10.1145\/181014.192323"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Chatterjee, P., Gopalakrishnan, G.: Towards a formal model of shared memory consistency for intel itaniumtm. In: Proc. 2001 IEEE International Conference on Computer Design (ICCD), September 2001, pp. 515\u2013518 (2001)","DOI":"10.1109\/ICCD.2001.955081"},{"issue":"3","key":"12_CR4","doi-asserted-by":"publisher","first-page":"463","DOI":"10.1145\/78969.78972","volume":"12","author":"M. Herlihy","year":"1990","unstructured":"Herlihy, M., Wing, J.: Linearizability: A correctness condition for concurrent objects. ACM Trans. on Programming Languages and Systems\u00a012(3), 463\u2013492 (1990)","journal-title":"ACM Trans. on Programming Languages and Systems"},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Higham, L., Jackson, L., Kawash, J.: Specifying memory consistency of write buffer multiprocessors. ACM Trans. on Computer Systems (in press)","DOI":"10.1145\/1189736.1189737"},{"key":"12_CR6","doi-asserted-by":"crossref","unstructured":"Higham, L., Jackson, L., Kawash, J.: Capturing register and control dependence in memory consistency models with applications to the Itanium architecture. Technical Report 2006-837-30, Department of Computer Science, The University of Calgary (July 2006)","DOI":"10.1007\/11864219_12"},{"key":"12_CR7","doi-asserted-by":"crossref","unstructured":"Higham, L., Jackson, L., Kawash, J.: Programmer-centric conditions for Itanium memory consistency. Technical Report 2006-838-31, Department of Computer Science, The University of Calgary (July 2006)","DOI":"10.1007\/11947950_7"},{"key":"12_CR8","doi-asserted-by":"crossref","unstructured":"Higham, L., Kawash, J.: Tight bounds for critical sections on processor consistent platforms. IEEE Trans. on Parallel and Distributed Systems (in press)","DOI":"10.1109\/TPDS.2006.146"},{"key":"12_CR9","doi-asserted-by":"crossref","unstructured":"Higham, L., Kawash, J.: Critical sections and producer\/consumer queues in weak memory systems. In: Proc. 1997 Int\u2019l. Symp. on Parallel Architectures, Algorithms, and Networks, pp. 56\u201363 (December 1997)","DOI":"10.1109\/ISPAN.1997.645055"},{"key":"12_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"201","DOI":"10.1007\/BFb0056484","volume-title":"Distributed Computing","author":"L. Higham","year":"1998","unstructured":"Higham, L., Kawash, J.: Java: Memory consistency and process coordination (extended abstract). In: Kutten, S. (ed.) DISC 1998. LNCS, vol.\u00a01499, pp. 201\u2013215. Springer, Heidelberg (1998)"},{"key":"12_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"355","DOI":"10.1007\/3-540-44467-X_32","volume-title":"High Performance Computing - HiPC 2000","author":"L. Higham","year":"2000","unstructured":"Higham, L., Kawash, J.: Memory consistency and process coordination for SPARC multiprocessors. In: Prasanna, V.K., Vajapeyam, S., Valero, M. (eds.) HiPC 2000. LNCS, vol.\u00a01970, pp. 355\u2013366. Springer, Heidelberg (2000)"},{"key":"12_CR12","unstructured":"Intel Corporation. A formal specification of the intel itanium processor family memory ordering (October 2002), http:\/\/www.intel.com\/"},{"key":"12_CR13","unstructured":"Intel Corporation. Intel Architecture Architecture Software Developer\u2019s Manual: Volume 3: Instruction Set Reference. Intel Corporation (October 2002)"},{"key":"12_CR14","unstructured":"Intel Corporation. Intel itanium architecture software developer\u2019s manual, vol. 2, System architecture (October 2002), http:\/\/www.intel.com\/"},{"key":"12_CR15","unstructured":"Jackson, L.: Complete framework for memory consistency with applications to Itanium multiprocessors. Ph.D. Dissertation (in preparation)"},{"key":"12_CR16","doi-asserted-by":"crossref","unstructured":"Joshi, R., Lamport, L., Matthews, J., Tasiran, S., Tuttle, M., Yu, Y.: Checking cache-coherence protocols with tla (2003)","DOI":"10.1023\/A:1022969405325"},{"issue":"9","key":"12_CR17","doi-asserted-by":"publisher","first-page":"690","DOI":"10.1109\/TC.1979.1675439","volume":"C-28","author":"L. Lamport","year":"1979","unstructured":"Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. on Computers\u00a0C-28(9), 690\u2013691 (1979)","journal-title":"IEEE Trans. on Computers"},{"key":"12_CR18","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/978-3-540-39724-3_9","volume-title":"Correct Hardware Design and Verification Methods","author":"Y. Yang","year":"2003","unstructured":"Yang, Y., Gopalakrishnan, G.C., Lindstrom, G., Slind, K.: Analyzing the intel itanium memory ordering rules using logic programming and SAT. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol.\u00a02860, pp. 81\u201395. Springer, Heidelberg (2003)"}],"container-title":["Lecture Notes in Computer Science","Distributed Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11864219_12.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,11]],"date-time":"2025-01-11T03:23:34Z","timestamp":1736565814000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11864219_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540446248","9783540446279"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/11864219_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}