{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T14:23:58Z","timestamp":1725891838980},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540472377"},{"type":"electronic","value":"9783540472384"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11901914_19","type":"book-chapter","created":{"date-parts":[[2006,10,10]],"date-time":"2006-10-10T01:21:43Z","timestamp":1160443303000},"page":"229-244","source":"Crossref","is-referenced-by-count":0,"title":["Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis"],"prefix":"10.1007","author":[{"given":"Tomohiro","family":"Yoneda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris J.","family":"Myers","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"3","key":"19_CR1","first-page":"315","volume":"E80-D","author":"J. Cortadella","year":"1997","unstructured":"Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. on Information and Systems\u00a0E80-D(3), 315\u2013325 (1997)","journal-title":"IEICE Trans. on Information and Systems"},{"key":"19_CR2","doi-asserted-by":"crossref","unstructured":"Beerel, P.A., Myers, C.J., Meng, T.H.-Y.: Covering conditions and algorithms for the synthesis of speed-independent circuits. IEEE Trans. on Computer-Aided Design (1998)","DOI":"10.1109\/43.700719"},{"key":"19_CR3","unstructured":"Fuhrer, R.M., Nowick, S.M., Theobald, M., Jha, N.K., Lin, B., Plana, L.: Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous machines. Technical Report TR CUCS-020-99, Columbia University, NY (1999)"},{"key":"19_CR4","unstructured":"Chu, T.-A.: Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science (1987)"},{"key":"19_CR5","first-page":"135","volume-title":"Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems","author":"T. Yoneda","year":"2004","unstructured":"Yoneda, T., Onda, H., Myers, C.: Synthesis of speed independent circuits based on decomposition. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 135\u2013145. IEEE Computer Society Press, Los Alamitos (2004)"},{"key":"19_CR6","doi-asserted-by":"crossref","unstructured":"Carmona, J., Cortadella, J.: ILP models for the synthesis of asynchronous control circuits. In: Proc. of the IEEE\/ACM International Conference on Computer Aided Design, pp. 818\u2013825 (2003)","DOI":"10.1109\/ICCAD.2003.159771"},{"issue":"2","key":"19_CR7","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1109\/4.902762","volume":"35","author":"K. Stevens","year":"2001","unstructured":"Stevens, K., Rotem, S., Ginosar, R., Beerel, P., Myers, C., Yun, K., Kol, R., Dike, C., Roncken, M.: An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits\u00a035(2), 217\u2013228 (2001)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"19_CR8","first-page":"46","volume-title":"Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems","author":"I. Sutherland","year":"2001","unstructured":"Sutherland, I., Fairbanks, S.: GasP: A minimal FIFO control. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 46\u201353. IEEE Computer Society Press, Los Alamitos (2001)"},{"key":"19_CR9","unstructured":"Yoneda, T., Myers, C.: Synthesis of timed circuits based on decomposition. NII Technical Report, NII-2006-001E (2006)"},{"key":"19_CR10","volume-title":"Stepwise refinements for transitions and places","author":"I. Suzuki","year":"1982","unstructured":"Suzuki, I., Murata, T.: Stepwise refinements for transitions and places. Springer, New York (1982)"},{"key":"19_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"19","DOI":"10.1007\/BFb0016204","volume-title":"Advances in Petri Nets 1985","author":"G. Berthelot","year":"1986","unstructured":"Berthelot, G.: Checking properties of nets using transformations. In: Rozenberg, G. (ed.) APN 1985. LNCS, vol.\u00a0222, pp. 19\u201340. Springer, Heidelberg (1986)"},{"issue":"4","key":"19_CR12","doi-asserted-by":"publisher","first-page":"541","DOI":"10.1109\/5.24143","volume":"77","author":"T. Murata","year":"1989","unstructured":"Murata, T.: Petri nets: Properties, analysis, and applications. Proceedings of the IEEE\u00a077(4), 541\u2013580 (1989)","journal-title":"Proceedings of the IEEE"},{"key":"19_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"152","DOI":"10.1007\/3-540-36190-1_5","volume-title":"Concurrency and Hardware Design","author":"W. Vogler","year":"2002","unstructured":"Vogler, W., Wollowski, R.: Decomposition in asynchronous circuit design. In: Cortadella, J., Yakovlev, A., Rozenberg, G. (eds.) Concurrency and Hardware Design. LNCS, vol.\u00a02549, pp. 152\u2013190. Springer, Heidelberg (2002)"},{"key":"19_CR14","doi-asserted-by":"crossref","unstructured":"Zheng, H., Mercer, E., Myers, C.J.: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on Computer-Aided Design 22(9) (2003)","DOI":"10.1109\/TCAD.2003.816214"},{"key":"19_CR15","unstructured":"Zheng, H.: Modular Synthesis and Verification of Timed Circuits Using Automatic Abstraction. PhD thesis, University of Utah (2001)"},{"key":"19_CR16","unstructured":"Myers, C.J.: Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits. PhD thesis, Dept. of Elec. Eng., Stanford University (1995)"},{"key":"19_CR17","unstructured":"Yoneda, T., Mercer, E.G., Myers, C.J.: Modular synthesis of timed circuits using partial order reduction. In: Proc. of the 10th Workshop on Synthesis And System Integration of Mixed Technologies, pp. 127\u2013134 (2001)"},{"key":"19_CR18","unstructured":"Mercer, E.G., Myers, C.J., Yoneda, T.: Improved POSET timing analysis in timed Petri nets. In: Proc. of the 10th Workshop on Synthesis And System Integration of Mixed Technologies, pp. 151\u2013158 (2001)"},{"key":"19_CR19","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"677","DOI":"10.1007\/978-3-540-30140-0_60","volume-title":"Algorithms \u2013 ESA 2004","author":"L. Georgiadis","year":"2004","unstructured":"Georgiadis, L., Tarjan, R.E., Triantafyllis, S., August, D.: Finding dominators in practice. In: Albers, S., Radzik, T. (eds.) ESA 2004. LNCS, vol.\u00a03221, pp. 677\u2013688. Springer, Heidelberg (2004)"},{"key":"19_CR20","doi-asserted-by":"crossref","first-page":"178","DOI":"10.1109\/ASYNC.2005.22","volume-title":"Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems","author":"T. Yoneda","year":"2005","unstructured":"Yoneda, T., Matsumoto, A., Kato, M., Myers, C.: High level synthesis of timed asynchronous circuits. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 178\u2013189. IEEE Computer Society Press, Los Alamitos (2005)"}],"container-title":["Lecture Notes in Computer Science","Automated Technology for Verification and Analysis"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11901914_19.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,17]],"date-time":"2020-11-17T14:56:12Z","timestamp":1605624972000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11901914_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540472377","9783540472384"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/11901914_19","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}