{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:54:08Z","timestamp":1725472448431},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540680673"},{"type":"electronic","value":"9783540680703"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11946441_23","type":"book-chapter","created":{"date-parts":[[2006,11,18]],"date-time":"2006-11-18T10:52:47Z","timestamp":1163847167000},"page":"207-218","source":"Crossref","is-referenced-by-count":1,"title":["Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels"],"prefix":"10.1007","author":[{"given":"Hiroki","family":"Matsutani","sequence":"first","affiliation":[]},{"given":"Michihiro","family":"Koibuchi","sequence":"additional","affiliation":[]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"issue":"1","key":"23_CR1","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.976921","volume":"35","author":"L. Benini","year":"2002","unstructured":"Benini, L., Micheli, G.D.: Networks on Chips: A New SoC Paradigm. IEEE Computer\u00a035(1), 70\u201378 (2002)","journal-title":"IEEE Computer"},{"key":"23_CR2","doi-asserted-by":"crossref","unstructured":"Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proceedings of the Design Automation Conference, pp. 684\u2013689 (2001)","DOI":"10.1109\/DAC.2001.935594"},{"issue":"7","key":"23_CR3","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/MC.2004.65","volume":"37","author":"D. Burger","year":"2004","unstructured":"Burger, D., et al.: Scaling to the End of Silicon with EDGE Architectures. IEEE Computer\u00a037(7), 44\u201355 (2004)","journal-title":"IEEE Computer"},{"issue":"7","key":"23_CR4","doi-asserted-by":"publisher","first-page":"711","DOI":"10.1109\/TVLSI.2004.830919","volume":"12","author":"J. Liang","year":"2004","unstructured":"Liang, J., et al.: An Architecture and Compiler for Scalable On-Chip Communication. IEEE Transactions on Very Large Scale Integration Systems\u00a012(7), 711\u2013726 (2004)","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"issue":"2","key":"23_CR5","doi-asserted-by":"publisher","first-page":"25","DOI":"10.1109\/MM.2002.997877","volume":"22","author":"M.B. Taylor","year":"2002","unstructured":"Taylor, M.B., et al.: The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs. IEEE Micro\u00a022(2), 25\u201335 (2002)","journal-title":"IEEE Micro"},{"key":"23_CR6","unstructured":"Matsutani, H., Koibuchi, M., Amano, H.: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. In: Proceedings of the International Conference on Parallel and Distributed Computing Systems, pp. 24\u201331 (2006)"},{"issue":"7","key":"23_CR7","doi-asserted-by":"publisher","first-page":"693","DOI":"10.1109\/TPDS.2002.1019859","volume":"13","author":"J. Flich","year":"2002","unstructured":"Flich, J., Lopez, P., Malumbres, M.P., Duato, J.: Boosting the Performance of Myrinet Networks. IEEE Transactions on Parallel and Distributed Systems\u00a013(7), 693\u2013709 (2002)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"23_CR8","doi-asserted-by":"crossref","unstructured":"Puente, V., Beivide, R., Gregorio, J.A., Prellezo, J.M., Duato, J., Izu, C.: Adaptive Bubble Router: A Design to Improve Performance in Torus Networks. In: Proceedings of the International Conference on Parallel Processing, pp. 58\u201367 (1999)","DOI":"10.1109\/ICPP.1999.797388"},{"key":"23_CR9","volume-title":"Principles and Practices of Interconnection Networks","author":"W.J. Dally","year":"2004","unstructured":"Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2004)"}],"container-title":["Lecture Notes in Computer Science","Parallel and Distributed Processing and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11946441_23","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,11]],"date-time":"2019-03-11T01:41:07Z","timestamp":1552268467000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11946441_23"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540680673","9783540680703"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/11946441_23","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}