{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,9]],"date-time":"2024-09-09T14:37:22Z","timestamp":1725892642399},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540681397"},{"type":"electronic","value":"9783540681403"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006]]},"DOI":"10.1007\/11947950_7","type":"book-chapter","created":{"date-parts":[[2007,2,26]],"date-time":"2007-02-26T12:26:54Z","timestamp":1172492814000},"page":"58-69","source":"Crossref","is-referenced-by-count":10,"title":["Programmer-Centric Conditions for Itanium Memory Consistency"],"prefix":"10.1007","author":[{"given":"Lisa","family":"Higham","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"LillAnne","family":"Jackson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jalal","family":"Kawash","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"5","key":"7_CR1","doi-asserted-by":"publisher","first-page":"502","DOI":"10.1109\/TPDS.2003.1199067","volume":"14","author":"H. Attiya","year":"2003","unstructured":"Attiya, H., Shurek, G.: Information-flow models for shared memory with an application to the PowerPC architecture. IEEE Trans. on Parallel and Distributed Systems\u00a014(5), 502\u2013515 (2003)","journal-title":"IEEE Trans. on Parallel and Distributed Systems"},{"key":"7_CR2","doi-asserted-by":"crossref","unstructured":"Adve, S.V., Gharachorloo, K.: Shared memory consistency models: A tutorial. IEEE Computer, 66\u201376 (1996)","DOI":"10.1109\/2.546611"},{"key":"7_CR3","doi-asserted-by":"crossref","unstructured":"Arvind, Maessen, J.-W.: Memory model = instruction reordering + store atomicity. In: Proc. ISCA (2006) (to appear)","DOI":"10.1109\/ISCA.2006.26"},{"key":"7_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"401","DOI":"10.1007\/978-3-540-27813-9_31","volume-title":"Computer Aided Verification","author":"G. Gopalakrishnan","year":"2004","unstructured":"Gopalakrishnan, G., Yang, Y., Sivaraj, H.: QB or not QB: An efficient execution verification tool for memory orderings. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol.\u00a03114, pp. 401\u2013413. Springer, Heidelberg (2004)"},{"key":"7_CR5","unstructured":"Higham, L., Jackson, L.: Porting between Itanium and Sparc multiprocessing systems. In: 18th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA 2006 (2006) (to appear)"},{"key":"7_CR6","doi-asserted-by":"crossref","unstructured":"Higham, L., Jackson, L., Kawash, J.: Specifying memory consistency of write buffer multiprocessors. ACM Trans. on Computer Systems (to appear)","DOI":"10.1145\/1189736.1189737"},{"key":"7_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"164","DOI":"10.1007\/11864219_12","volume-title":"Distributed Computing","author":"L. Higham","year":"2006","unstructured":"Higham, L., Jackson, L., Kawash, J.: Capturing register and control dependence in memory consistency models with applications to the itanium architecture. In: Dolev, S. (ed.) DISC 2006. LNCS, vol.\u00a04167, pp. 164\u2013178. Springer, Heidelberg (2006); A longer version is available as Technical Report 2006-837-30, Department of Computer, The University of Calgary, Canada"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Higham, L., Jackson, L., Kawash, J.: Programmer-centric conditions for Itanium memory consistency. Technical Report 2006-838-31, Department of Computer Science, The University of Calgary (July 2006)","DOI":"10.1007\/11947950_7"},{"key":"7_CR9","unstructured":"Intel Corporation. A formal specification of the Intel Itanium processor family memory ordering (October 2002), http:\/\/www.intel.com\/design\/itanium\/downloads\/251429.htm\/"},{"key":"7_CR10","doi-asserted-by":"crossref","unstructured":"Joshi, R., Lamport, L., Matthews, J., Tasiran, S., Tuttle, M., Yu, Y.: Checking cache-coherence protocols with tla (2003)","DOI":"10.1023\/A:1022969405325"},{"key":"7_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"81","DOI":"10.1007\/978-3-540-39724-3_9","volume-title":"Correct Hardware Design and Verification Methods","author":"Y. Yang","year":"2003","unstructured":"Yang, Y., Gopalakrishnan, G., Lindstrom, G., Slind, K.: Analyzing the Intel Itanium memory ordering rules using logic programming and SAT. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol.\u00a02860, pp. 81\u201395. Springer, Heidelberg (2003)"},{"key":"7_CR12","doi-asserted-by":"crossref","unstructured":"Yang, Y., Gopalakrishnan, G., Lindstrom, G., Slind, K.: Nemos: A framework for axiomatic and executable specifications of memory consistency models. In: Proc. 18th International Parallel and Distributed Processing Symposium (IPDPS 2004) (April 2004)","DOI":"10.1109\/IPDPS.2004.1302944"}],"container-title":["Lecture Notes in Computer Science","Distributed Computing and Networking"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/11947950_7.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T07:19:15Z","timestamp":1619507955000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/11947950_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006]]},"ISBN":["9783540681397","9783540681403"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/11947950_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2006]]}}}