{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T22:51:26Z","timestamp":1725663086034},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540167662"},{"type":"electronic","value":"9783540387466"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1986]]},"DOI":"10.1007\/3-540-16766-8_12","type":"book-chapter","created":{"date-parts":[[2012,2,25]],"date-time":"2012-02-25T18:53:26Z","timestamp":1330196006000},"page":"133-143","source":"Crossref","is-referenced-by-count":0,"title":["Some new results on a restricted channel routing problem"],"prefix":"10.1007","author":[{"given":"E.","family":"Lodi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Pagli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2005,6,1]]},"reference":[{"key":"12_CR1","doi-asserted-by":"crossref","unstructured":"Hashimoto A. and Stevens J. \"Wire Routing by Optimizing Channel Assignment within Large Apertures\", Proc. 8-th Design Automation Workshop, IEEE (1971), 214\u2013224.","DOI":"10.1145\/800158.805069"},{"issue":"4","key":"12_CR2","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/MC.1974.6323494","volume":"7","author":"D. Hightower","year":"1974","unstructured":"Hightower D. \"The Interconnection Problem: A Tutorial\", Computer 7, 4 (April 1974), 18\u201332.","journal-title":"Computer"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Deutsch D. N. \"A \u2018Dogleg\u2019 Channel Router\", Proc. 19-th Design Automation Conference, IEEE (1976), 425\u2013433.","DOI":"10.1145\/800146.804843"},{"issue":"5","key":"12_CR4","doi-asserted-by":"crossref","first-page":"427","DOI":"10.1109\/TC.1984.1676459","volume":"33","author":"F. P. Preparata","year":"1984","unstructured":"Preparata, F. P. and Lipsky W. \"Optimal Three-Layer Channel Routing\", IEEE Transections on Computers, 33, 5 (May 1984), 427\u2013437.","journal-title":"IEEE Transections on Computers"},{"key":"12_CR5","doi-asserted-by":"crossref","unstructured":"Kawamoto T. and Kajitani Y. \"The Minimum Width Routing of a 2-Row 2-Layer Polycell-Layout\", Proc. 16-th Design Automation Conference, IEEE (1979), 290\u2013296.","DOI":"10.1109\/DAC.1979.1600121"},{"key":"12_CR6","unstructured":"Szymanski T. \"Dogleg Channel Routing is NP-complete\", to appear."},{"key":"12_CR7","doi-asserted-by":"crossref","unstructured":"Rivest R. L., Baratz A. E. and Miller G. \"Provably Good Channel Routing Algorithms\", Proc. CMU Conference on VLSI Systems and Computations, (1981), 153\u2013159.","DOI":"10.1007\/978-3-642-68402-9_18"},{"key":"12_CR8","first-page":"205","volume":"2","author":"B. S. Baker","year":"1984","unstructured":"Baker B. S., S. N. Bhatt and T. Leighton \"An Approximation Algorithm for Manhattan Routing\", Advances in Computing Research, 2, (1984), 205\u2013229.","journal-title":"Advances in Computing Research"},{"key":"12_CR9","doi-asserted-by":"crossref","unstructured":"Brown D. and Rivest R. L. \"New Lower Bounds on Channel Width\", Proc. CMU Conference on VLSI Systems and Computations, (Computer Science Press 1981), 178\u2013185.","DOI":"10.1007\/978-3-642-68402-9_20"},{"issue":"1","key":"12_CR10","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/TCAD.1982.1269993","volume":"CAD-1","author":"T. Yoshimura","year":"1982","unstructured":"Yoshimura T. and Kuh E. \"Efficient Algorithms for Channel Routing\", IEEE Transections on Computer, CAD-1, 1 (January 1982), 25\u201335.","journal-title":"IEEE Transections on Computer"},{"key":"12_CR11","unstructured":"Lodi E. and Preparata F. P. \"A Heuristic for Manahattan Routing\" to appear."},{"key":"12_CR12","unstructured":"Kerninghan B. W., Schweickert D. G., Persky G. \"An Optimum Channel-Routing Algorithm for Polycell Layouts of Integrated Circuits\", Proc. 11-th DA Workshop, 1973, 26\u201346."}],"container-title":["Lecture Notes in Computer Science","VLSI Algorithms and Architectures"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-16766-8_12.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,31]],"date-time":"2021-12-31T01:47:57Z","timestamp":1640915277000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-16766-8_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1986]]},"ISBN":["9783540167662","9783540387466"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/3-540-16766-8_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1986]]}}}