{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:47:53Z","timestamp":1725551273790},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540001164"},{"type":"electronic","value":"9783540361268"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2002]]},"DOI":"10.1007\/3-540-36126-x_21","type":"book-chapter","created":{"date-parts":[[2010,3,29]],"date-time":"2010-03-29T21:55:19Z","timestamp":1269899719000},"page":"342-359","source":"Crossref","is-referenced-by-count":1,"title":["Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries"],"prefix":"10.1007","author":[{"given":"Steve","family":"McKeever","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Luk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arran","family":"Derbyshire","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,11,5]]},"reference":[{"key":"21_CR1","doi-asserted-by":"crossref","unstructured":"P. Bjesse, K. Claessen, M. Sheeran and S. Singh, \u201cLava: Hardware design in Haskell\u201d, Proc. ACM Int. Conf. Functional Programming (ICFP\u201998), ACM Press, 1998.","DOI":"10.1145\/289423.289440"},{"key":"21_CR2","doi-asserted-by":"crossref","unstructured":"F. Dupont-De-Dinechin, W. Luk and S.W. McKeever, \u201cTowards portable hierarchical placement for FPGAs\u201d, INRIA Report 3776, 1999.","DOI":"10.1145\/296399.296528"},{"key":"21_CR3","doi-asserted-by":"crossref","unstructured":"S. Guo and W. Luk, \u201cAn Integrated system for developing regular array design\u201d, Journal of Systems Architecture, Vol. 47, 2001.","DOI":"10.1016\/S1383-7621(00)00052-7"},{"key":"21_CR4","unstructured":"N. Jones, C. Gomard and P. Sestoft, Partial Evaluation and Automatic Program Generation, Prentice Hall International Series in Computer Science, 1993."},{"key":"21_CR5","unstructured":"W. Luk, \u201cA declarative approach to incremental custom computing\u201d, in Proc. Symp. on FPGAs for Custom Computing Machines, IEEE Computer Society Press, 1995."},{"key":"21_CR6","series-title":"Lect Notes Comput Sci","volume-title":"Field-Programmable Logic and Applications","author":"W. Luk","year":"1996","unstructured":"W. Luk, S. Guo, N. Shirazi and N. Zhuang, \u201cA framework for developing parametrised FPGA libraries\u201d, in Field-Programmable Logic and Applications, LNCS 1142, Springer, 1996."},{"key":"21_CR7","unstructured":"W. Luk, T. Kean, A. Derbyshire, J. Gause, S.W. McKeever, O. Mencer and A. Yeow, \u201cParameterised Hardware Libraries for Programmable System-on-Chip Technology\u201d, in Canadian Journal of Electrical and Computer Engineering, Vol. 26, No. 3\/4, 2001."},{"key":"21_CR8","unstructured":"W. Luk and I. Page, \u201cParametrising designs for FPGAs\u201d, in FPGAs, Abingdon EE&CS Books, 1991."},{"key":"21_CR9","series-title":"Lect Notes Comput Sci","volume-title":"Field-Programmable Logic and Applications","author":"W. Luk","year":"1998","unstructured":"W. Luk and S.W. McKeever, \u201cPebble: a language for parametrised and reconfigurable hardware design\u201d, in Field-Programmable Logic and Applications, LNCS 1482, Springer, 1998."},{"key":"21_CR10","series-title":"Lect Notes Comput Sci","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44687-7_48","volume-title":"Field-Programmable Logic and Applications","author":"J. MacBeth","year":"2001","unstructured":"J. MacBeth and P. Lysaght, \u201cDynamically reconfigurable cores\u201d, in Field-Programmable Logic and Applications, LNCS 2147, Springer, 2001."},{"key":"21_CR11","doi-asserted-by":"crossref","unstructured":"N. McKay, T. Melham, K.W. Susanto and S. Singh, \u201cDynamic specialisation of XC6200 FPGAs by partial evaluation\u201d, in Proc. Symp. on FPGAs for Custom Computing Machines, IEEE Computer Society Press, 1998.","DOI":"10.1007\/BFb0055257"},{"key":"21_CR12","series-title":"Lect Notes Comput Sci","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44798-9_19","volume-title":"Correct Hardware Design and Verification Methods","author":"S.W. McKeever","year":"2001","unstructured":"S.W. McKeever and W. Luk, \u201cTowards provably-correct hardware compilation tools based on pass separation techniques\u201d, in Correct Hardware Design and Verification Methods, LNCS 2144, Springer, 2001."},{"key":"21_CR13","doi-asserted-by":"crossref","unstructured":"S.W. McKeever and W. Luk, \u201cA declarative framework for developing parametrised hardware libraries\u201d, in Proc. 8th Int. Conf. on Electronics, Circuits and Systems, IEEE, 2001.","DOI":"10.1109\/ICECS.2001.957532"},{"key":"21_CR14","unstructured":"C. Patterson, \u201cHigh Performance DES Encryption in Virtex FPGAs using JBits\u201d, Proc. Symp. on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 2000."},{"key":"21_CR15","doi-asserted-by":"crossref","unstructured":"R. Sharp and O. Rasmussen, \u201cThe T-Ruby design system\u201d, Formal Methods in System Design, Vol. 11, No. 3, October, 1997.","DOI":"10.1023\/A:1008603713967"},{"key":"21_CR16","doi-asserted-by":"crossref","unstructured":"N. Shirazi, W. Luk and P.Y.K. Cheung, \u201cFramework and tools for run-time reconfigurable designs\u201d, IEE Proc. Comput. Digit. Tech., Vol. 147, No. 3, May 2000.","DOI":"10.1049\/ip-cdt:20000486"},{"key":"21_CR17","unstructured":"S. Singh, \u201cArchitectural descriptions for FPGA circuits\u201d, in Proc. Symp. on FPGAs for Custom Computing Machines, IEEE Computer Society Press, 1995."},{"key":"21_CR18","doi-asserted-by":"crossref","unstructured":"S. Singh, \u201cDeath of the RLOC?\u201d, in Proc. Symp. on Field-Programmable Custom Computing Machines, IEEE Computer Society Press, 2000.","DOI":"10.1109\/FPGA.2000.903401"},{"key":"21_CR19","series-title":"Lect Notes Comput Sci","volume-title":"Proc. Cryptographic Hardware and Embedded Systems","author":"S. Trimberger","year":"2000","unstructured":"S. Trimberger, R. Pang and A. Singh, \u201cA 12 Gbps DES encryptor\/decryptor core in an FPGA\u201d, in Proc. Cryptographic Hardware and Embedded Systems, LNCS 1965, Springer, 2000."},{"key":"21_CR20","unstructured":"Q. Wang and D.M. Lewis, \u201cAutomated field-programmable compute accelerator design using partial evaluation\u201d, in Proc. Symp. on FPGAs for Custom Computing Machines, IEEE Computer Society Press, 1997."}],"container-title":["Lecture Notes in Computer Science","Formal Methods in Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-36126-X_21","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,27]],"date-time":"2019-05-27T19:26:48Z","timestamp":1558985208000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-36126-X_21"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002]]},"ISBN":["9783540001164","9783540361268"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/3-540-36126-x_21","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2002]]}}}