{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:18:45Z","timestamp":1761675525488,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540007302"},{"type":"electronic","value":"9783540365532"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/3-540-36553-2_33","type":"book-chapter","created":{"date-parts":[[2007,10,7]],"date-time":"2007-10-07T03:36:26Z","timestamp":1191728186000},"page":"365-376","source":"Crossref","is-referenced-by-count":14,"title":["Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware"],"prefix":"10.1007","author":[{"given":"Snorre","family":"Aunet","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Morten","family":"Hartmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2003,6,24]]},"reference":[{"doi-asserted-by":"crossref","unstructured":"P. Hasler, T. S. Lande Overview of Floating-Gate Devices, Circuits and Systems, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, January 2001.","key":"33_CR1","DOI":"10.1109\/TCSII.2001.913180"},{"unstructured":"S. Aunet, Y. Berg, T. S\u00e6ther A New 2-MOSFET Universal Floating-Gate Element for Reconfigurable Digital LogicProceedings of the 19th IEEE Norchip Conference, Kista, Sweden, 12\u201313 November 2001, pp. 240\u2013245.","key":"33_CR2"},{"doi-asserted-by":"crossref","unstructured":"T. Shibata, T. Ohmi An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, Technical Digest, International Electron Devices Meeting, 1991.","key":"33_CR3","DOI":"10.1109\/16.137325"},{"doi-asserted-by":"crossref","unstructured":"T. S. Lande, D. T. Wisland, T. S\u00e6ther, Y. Berg FLOGIC\u2014Floating-Gate Logic for Low-Power Operation Proceedings of the 3rd IEEE International Conference on Electronics, Circuits and Systems, 1996, pp 1041\u20131044.","key":"33_CR4","DOI":"10.1109\/ICECS.1996.584565"},{"doi-asserted-by":"crossref","unstructured":"Y. Berg, T. S. Lande, S. N\u00e6ss Low-Voltage Floating-Gate Current Mirrors Proceedings of the the Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC), Portland, OR, USA, 7\u201310 Sept. 1997, pp 21\u201324.","key":"33_CR5","DOI":"10.1109\/ASIC.1997.616971"},{"issue":"7","key":"33_CR6","doi-asserted-by":"publisher","first-page":"930","DOI":"10.1109\/82.775389","volume":"46","author":"Y. Berg","year":"1999","unstructured":"Y. Berg, D. T. Wisland, T. S. Lande Ultra Low-Voltage\/Low-Power Digital Floating-Gate Circuits IEEE Transactions on Circuits and Systems II, analog and digital signal processing, Vol. 46, Issue 7, pp. 930\u2013936, July 1999.","journal-title":"IEEE Transactions on Circuits and Systems II, analog and digital signal processing"},{"unstructured":"S. Aunet Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS Dissertation for the degree of doktor ingeni\u00f8r, Norwegian University of Science and Technology, ISBN 82-471-5447-1, 2002.","key":"33_CR7"},{"unstructured":"Austria Mikro Systeme International AG 0.6 um CMOS CUP Process Parameters Document no. 9933011, Rev. B, Oct. 1998.","key":"33_CR8"},{"issue":"7","key":"33_CR9","first-page":"930","volume":"46","author":"Y. Berg","year":"1999","unstructured":"Y. Berg, D. T. Wisland, T. S. Lande Ultra Low-Voltage\/Low-Power Digital Floating-Gate Circuits IEEE Transactions on Circuits and Systems II, analog and digital signal processing, Vol. 46, Issue 7, pp. 930\u2013936, July 1999.","journal-title":"Ultra Low-Voltage\/Low-Power Digital Floating-Gate Circuits"},{"doi-asserted-by":"crossref","unstructured":"J. Rabaey, M. Pedram, P. Landman Low Power Design Methodologiesin J. Rabaey, M. Pedram (editors), Low Power Design Methodologies, Kluwer Academic Publishers, 1997.","key":"33_CR10","DOI":"10.1007\/978-1-4615-2307-9"},{"unstructured":"S. Aunet, Y. Berg, O. Tjore, \u00d8. N\u00e6ss, T. S\u00e6ther Four-MOSFET Floating-Gate UV-Programmable Elements for Multifunction Binary Logic Proceedings of the 5th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, FL, USA, Volume 3,2001, pp 141\u2013144.","key":"33_CR11"},{"unstructured":"P. P. Gelsinger Microprocessors for the New Millennium: Challenges, Opportunities, and New Frontiers Digest of technical papers, IEEE International Solid-State Circuits Conference, 2001, pp. 22\u201325.","key":"33_CR12"},{"unstructured":"G. Gilder, B. Swanson Seattle Sunburst Gilder Technology Report, 2002.","key":"33_CR13"},{"unstructured":"K. R. Laker, W. M. C. Sansen Design of analog integrated circuits and systems McGraw-Hill International Editions, ISBN 0-07-113458-1, 1994.","key":"33_CR14"},{"unstructured":"R. Bahr A Design of Linear Four Quadrant Analog Multipliers Using Floating-Gate Transistors thesis for the cand. scient. degree, University of Oslo, Faculty of Mathematics and Natural Sciences, Department of informatics, May 2001.","key":"33_CR15"},{"unstructured":"K. Y. Siu, J. Bruck Neural Computation of Arithmetic Functions Proceedings of the IEEE, No. 10, pp. 1669\u20131675, October 1990.","key":"33_CR16"},{"unstructured":"V. Bohossian Neural Logic: Theory and Implementation Dissertation for the Ph.D. degree, California Institute of Technology, 1998.","key":"33_CR17"},{"doi-asserted-by":"crossref","unstructured":"D. Hammerstrom Computational Neurobiology Meets Semiconductor Engineering Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000, pp. 3\u201312.","key":"33_CR18","DOI":"10.1109\/ISMVL.2000.848593"},{"key":"33_CR19","first-page":"946","volume":"39","author":"K. Y. Siu","year":"1993","unstructured":"K. Y. Siu, J. Bruck, T. Kailath, T. Hofmeister Depth Efficient Neural Networks for Division and Related Problems IEEE Transactions on information theory, Vol. 39, No. 3, pp. 946\u2013956, May 1993.","journal-title":"Depth Efficient Neural Networks for Division and Related Problems"},{"unstructured":"T. Shibata Intelligent VLSI Systems Based on a Psychological Brain Model Proceedings of the 2000 IEEE International Symposium on Intelligent Signal Processing and Systems, pp 323\u2013332, Hawaii, U.S.A., November 5\u20138, 2000.","key":"33_CR20"}],"container-title":["Lecture Notes in Computer Science","Evolvable Systems: From Biology to Hardware"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-36553-2_33","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T12:39:20Z","timestamp":1737463160000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-36553-2_33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540007302","9783540365532"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/3-540-36553-2_33","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2003]]}}}