{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T21:39:58Z","timestamp":1725485998017},"publisher-location":"Berlin, Heidelberg","reference-count":23,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540009047"},{"type":"electronic","value":"9783540365792"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/3-540-36579-6_2","type":"book-chapter","created":{"date-parts":[[2007,6,7]],"date-time":"2007-06-07T18:15:58Z","timestamp":1181240158000},"page":"17-32","source":"Crossref","is-referenced-by-count":2,"title":["Early Control of Register Pressure for Software Pipelined Loops"],"prefix":"10.1007","author":[{"given":"Touati","family":"Sid-Ahmed-Ali","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christine","family":"Eisenbeis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2003,2,28]]},"reference":[{"key":"2_CR1","unstructured":"D. Berson, R. Gupta, and M. Soffa. URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures. In Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, pages 243\u2013254, Orlando, Florida, Jan. 1993."},{"issue":"7","key":"2_CR2","first-page":"379","volume":"4","author":"A. Darte","year":"1998","unstructured":"A. Darte, G.-A. Silber, and F. Vivien. Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling. Parallel Processing Letters, 4(7):379\u2013392, 1998.","journal-title":"Parallel Processing Letters"},{"issue":"2\u20133","key":"2_CR3","doi-asserted-by":"publisher","first-page":"191","DOI":"10.1016\/S0166-218X(99)00105-5","volume":"93","author":"D. Werra de","year":"1999","unstructured":"D. de Werra, C. Eisenbeis, S. Lelait, and B. Marmol. On a Graph-Theoretical Model for Cyclic Register Allocation. Discrete Applied Mathematics, 93(2\u20133):191\u2013203, July 1999.","journal-title":"Discrete Applied Mathematics"},{"key":"2_CR4","doi-asserted-by":"crossref","unstructured":"J. C. Dehnert, P. Y.-T. Hsu, and J. P. Bratt. Overlapped Loop Support in the Cydra 5. In Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems, pages 26\u201338, NewYork, Apr. 1989. ACM Press.","DOI":"10.1145\/70082.68185"},{"issue":"2","key":"2_CR5","doi-asserted-by":"crossref","first-page":"103","DOI":"10.1007\/BF03356744","volume":"24","author":"A. E. Eichenberger","year":"1996","unstructured":"A. E. Eichenberger, E. S. Davidson, and S. G. Abraham. Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling. International Journal of Parallel Programming, 24(2):103\u2013132, Apr. 1996.","journal-title":"International Journal of Parallel Programming"},{"key":"2_CR6","unstructured":"W. fen Lin, S. K. Reinhardt, and D. Burger. Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Nuevo Leone, Mexico, Jan. 2001."},{"issue":"6","key":"2_CR7","doi-asserted-by":"publisher","first-page":"697","DOI":"10.1142\/S0129054101000825","volume":"12","author":"D. Fimmel","year":"2001","unstructured":"D. Fimmel and J. Muller. Optimal Software Pipelining Under Resource Constraints. International Journal of Foundations of Computer Science (IJFCS), 12(6):697\u2013718, 2001.","journal-title":"International Journal of Foundations of Computer Science (IJFCS)"},{"key":"2_CR8","series-title":"Lect Notes Comput Sci","volume-title":"A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs","author":"L. J. Hendren","year":"1992","unstructured":"L. J. Hendren, G. R. Gao, E. R. Altman, and C. Mukerji. A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs. Lecture Notes in Computer Science, 641, 1992."},{"key":"2_CR9","doi-asserted-by":"crossref","unstructured":"R. Huff. Lifetime-Sensitive Modulo Scheduling. In PLDI 93, pages 258\u2013267, Albuquerque, New Mexico, June 1993.","DOI":"10.1145\/155090.155115"},{"key":"2_CR10","unstructured":"J. Janssen. Compilers Strategies for Transport Triggered Architectures. PhD thesis, Delft University, Netherlands, 2001."},{"key":"2_CR11","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1007\/BF01759032","volume":"6","author":"C. E. Leiserson","year":"1991","unstructured":"C. E. Leiserson and J. B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6:5\u201335, 1991.","journal-title":"Algorithmica"},{"key":"2_CR12","unstructured":"J. Llosa. Reducing the Impact of Register Pressure on Software Pipelined Loops. PhD thesis, Universitat Politecnica de Catalunya (Spain), 1996."},{"key":"2_CR13","doi-asserted-by":"crossref","unstructured":"Q. Ning and G. R. Gao. A Novel Framework of Register Allocation for Software Pipelining. In Conference Record of the Twentieth ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, pages 29\u201342, Charleston, South Carolina, Jan. 1993. ACM Press.","DOI":"10.1145\/158511.158519"},{"issue":"7","key":"2_CR14","doi-asserted-by":"publisher","first-page":"283","DOI":"10.1145\/143103.143141","volume":"27","author":"B. R. Rau","year":"1992","unstructured":"B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker. Register Allocation for Software Pipelined Loops. SIGPLAN Notices, 27(7):283\u2013299, July 1992. Proceedings of the ACM SIGPLAN\u2019 92 Conference on Programming Language Design and Implementation.","journal-title":"SIGPLAN Notices"},{"key":"2_CR15","doi-asserted-by":"crossref","unstructured":"F. Sanchez and J. Cortadella. RESIS: A New Methodology for Register Optimization in Software Pipelining. In Proceedings of Second International Euro-Par Conference, Euro-Par\u201996, Lyon, France, August 1996.","DOI":"10.1007\/BFb0024783"},{"key":"2_CR16","unstructured":"A. Sawaya. Pipeline Logiciel:D\u00e9couplage et Contraintes de Registres. PhD thesis, Universit\u00e9 de Versailles Saint-Quentin-En-Yvelines, Apr. 1997."},{"key":"2_CR17","unstructured":"Schlansker, B. Rau, and S. Mahlke. Achieving High Levels of instruction-Level Parallelism with Reduced Hardware Complexity. Technical Report HPL-96-120, Hewlet Packard, 1994."},{"issue":"11","key":"2_CR18","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1145\/291006.291015","volume":"33","author":"M. M. Strout","year":"1998","unstructured":"M. M. Strout, L. Carter, J. Ferrante, and B. Simon. Schedule-Independent Storage Mapping for Loops. ACM SIG-PLAN Notices, 33(11):24\u201333, Nov. 1998.","journal-title":"ACM SIG-PLAN Notices"},{"issue":"5","key":"2_CR19","doi-asserted-by":"publisher","first-page":"232","DOI":"10.1145\/381694.378852","volume":"36","author":"W. Thies","year":"2001","unstructured":"W. Thies, F. Vivien, J. Sheldon, and S. Amarasinghe. A Unified Framework for Schedule and Storage Optimization. ACM SIGPLAN Notices, 36(5):232\u2013242, May 2001.","journal-title":"ACM SIGPLAN Notices"},{"key":"2_CR20","doi-asserted-by":"crossref","unstructured":"S.-A.-A. Touati. EquiMax: A New Formulation of Acyclic Scheduling Problem for ILP Processors. In Interaction between Compilers and Computer Architectures. KluwerAcademic Publishers, 2001. ISBN 0-7923-7370-7.","DOI":"10.1007\/978-1-4757-3337-2_1"},{"key":"2_CR21","doi-asserted-by":"crossref","unstructured":"S.-A.-A. Touati. OptimalAcyclic Fine-Grain Schedule with Cache Effects for Embedded and Real Time Systems. In Proceedings of 9th nternational Symposium on Hardware\/Software Codesign, CODES, Copenhagen, Denmark, Apr. 2001. ACM.","DOI":"10.1145\/371636.371709"},{"key":"2_CR22","unstructured":"S.-A.-A. Touati. Register Pressure in Instruction Level Parallelisme. PhD thesis, Universit\u00e9 de Versailles, France, June 2002. ftp.inria.fr\/INRIA\/Projects\/a3\/touati\/thesis ."},{"key":"2_CR23","unstructured":"J. Wang, A. Krall, and M. A. Ertl. Decomposed Software Pipelining with Reduced Register Requirement. In Proceedings of the IFIP WG10.3Working Conference on Parallel Architectures and Compilation Techniques, PACT95, pages 277\u2013280, Limassol, Cyprus, June 1995."}],"container-title":["Lecture Notes in Computer Science","Compiler Construction"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-36579-6_2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,28]],"date-time":"2019-04-28T20:25:27Z","timestamp":1556483127000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-36579-6_2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540009047","9783540365792"],"references-count":23,"URL":"https:\/\/doi.org\/10.1007\/3-540-36579-6_2","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2003]]}}}