{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,23]],"date-time":"2026-08-23T14:45:09Z","timestamp":1787496309293,"version":"build-2736575974"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540411284","type":"print"},{"value":"9783540399995","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-39999-2_8","type":"book-chapter","created":{"date-parts":[[2007,9,2]],"date-time":"2007-09-02T20:22:39Z","timestamp":1188764559000},"page":"73-87","source":"Crossref","is-referenced-by-count":13,"title":["Loop Termination Prediction"],"prefix":"10.1007","author":[{"given":"Timothy","family":"Sherwood","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Brad","family":"Calder","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2001,4,6]]},"reference":[{"key":"8_CR1","doi-asserted-by":"crossref","unstructured":"A. Eden and T. Mudge. The YAGS branch prediction scheme. In 31st International Symposium on Microarchitecture, pages 69\u201377, December 1998. 85","DOI":"10.1109\/MICRO.1998.742770"},{"key":"8_CR2","doi-asserted-by":"crossref","unstructured":"A. Farcy, O. Temam, R. Espasa, and T. Juan. Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes. In 31st International Symposium on Microarchitecture, December 1998. 85","DOI":"10.1109\/MICRO.1998.742769"},{"key":"8_CR3","unstructured":"Gonzalez and Gonzalez. Control-flow speculation thorough value prediction for superscalar processors. In International Conference on Parallel Architectures and Compilation Techniques, October 1999. 85"},{"key":"8_CR4","doi-asserted-by":"crossref","unstructured":"T. Heil, Z. Smith, and J. E. Smith. Improving branch predictors by correlating on data values. In 32nd International Symposium on Microarchitecture, November 1999. 85","DOI":"10.1109\/MICRO.1999.809440"},{"key":"8_CR5","unstructured":"IBM. The PowerPC Architecture: A Specification for a New Family of RISC Processors. Morgan Kaufmann Publishers, 1994. 86"},{"key":"8_CR6","unstructured":"Intel. IA-64 Application Developer\u2019s Architecture Guide. Intel Corporation, Order Number 188-001 1999. 86"},{"key":"8_CR7","doi-asserted-by":"crossref","unstructured":"R. E. Kessler, E. J. McLellan, and D. A. Webb. The alpha 21264 microprocessor architecture. In International Conference on Computer Design, October 1998. 80","DOI":"10.1109\/ICCD.1998.727028"},{"key":"8_CR8","unstructured":"S. McFarling. Combining branch predictors. Technical Report TN-36, Digital Equipment Corporation, Western Research Lab, June 1993. 79"},{"issue":"4","key":"8_CR9","doi-asserted-by":"publisher","first-page":"396","DOI":"10.1109\/12.214687","volume":"42","author":"C. H. Perleberg","year":"1993","unstructured":"C. H. Perleberg and A. J. Smith. Branch target buffer design and optimization. IEEE Transactions on Computers, 42(4):396\u2013412, 1993. 76","journal-title":"IEEE Transactions on Computers"},{"key":"8_CR10","doi-asserted-by":"crossref","unstructured":"K. Skadron, P. Ahuja, M. Martonosi, and D. Clark. Improving prediction for procedure returns with return-address-stack repair mechanisms. In Proceedings of the 31st Annual International Symposium on Microarchitecture, pages 259\u2013271, December 1998. 77","DOI":"10.1109\/MICRO.1998.742787"},{"key":"8_CR11","unstructured":"J. E. Smith. A study of branch prediction strategies. In 8th Annual International Symposium of Computer Architecture, pages 135\u2013148. ACM, 1981. 73"},{"key":"8_CR12","doi-asserted-by":"crossref","unstructured":"A. Srivastava and A. Eustace. ATOM: A system for building customized program analysis tools. In Proceedings of the Conference on Programming Language Design and Implementation, pages 196\u2013205. ACM, 1994. 79","DOI":"10.1145\/178243.178260"},{"key":"8_CR13","doi-asserted-by":"crossref","unstructured":"J. Tubella and A. Gonzalez. Control speculation in multithreaded processors through dynamic loop detection. In 4th International Symposium on High Performance Computer Architecture, February 1998. 85","DOI":"10.1109\/HPCA.1998.650542"},{"key":"8_CR14","unstructured":"T. Yeh. Two-level adpative branch prediction and instruction fetch mechanisms for high performance superscalar processors. Ph.D. Dissertation, University of Michigan, 1993. 73"},{"key":"8_CR15","doi-asserted-by":"crossref","unstructured":"T. Yeh and Y. Patt. A comprehensive instruction fetch mechanism for a processor supporting speculative execution. In Proceedings of the 25th Annual International Symposium on Microarchitecture, pages 129\u2013139, December 1992. 76","DOI":"10.1109\/MICRO.1992.697009"},{"key":"8_CR16","doi-asserted-by":"crossref","unstructured":"T.-Y. Yeh and Y. Patt. Two-level adaptive branch prediction. In 18th Annual International Symposium on Computer Architecture, pages 51\u201361, May 1991. 73","DOI":"10.1145\/123465.123475"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-39999-2_8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,2,23]],"date-time":"2019-02-23T05:25:29Z","timestamp":1550899529000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-39999-2_8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540411284","9783540399995"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/3-540-39999-2_8","relation":{},"ISSN":["0302-9743"],"issn-type":[{"value":"0302-9743","type":"print"}],"subject":[],"published":{"date-parts":[[2000]]}}}