{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,15]],"date-time":"2024-09-15T13:31:45Z","timestamp":1726407105310},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540412199"},{"type":"electronic","value":"9783540409229"}],"license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-40922-x_25","type":"book-chapter","created":{"date-parts":[[2007,11,29]],"date-time":"2007-11-29T09:41:36Z","timestamp":1196329296000},"page":"442-459","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["The Semantics of Verilog Using Transition System Combinators"],"prefix":"10.1007","author":[{"given":"Gordon J.","family":"Pace","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,6,18]]},"reference":[{"key":"25_CR1","doi-asserted-by":"crossref","unstructured":"P. A. Abdulla, P. Bjesse, and N. E\u00e9n. Symbolic reachability analysis based on SAT-solvers. In TACAS00, 2000.","DOI":"10.1007\/3-540-46419-0_28"},{"key":"25_CR2","series-title":"Lect Notes Comput Sci","volume-title":"The Verus tool: A quantitative approach to the formal verification of real-time systems","author":"S. Campos","year":"1997","unstructured":"S. Campos, E. Clarke, and M. Minea. The Verus tool: A quantitative approach to the formal verification of real-time systems. Lecture Notes in Computer Science, 1254, 1997."},{"key":"25_CR3","unstructured":"S. Cheng, R. Brayton, R. York, K. Yelick, and A. Saldanha. Compiling Verilog into timed finite state machines. In 1995 IEEE International Verilog Conference (Washington 1995), pages 32\u201339. IEEE Press, 1995."},{"key":"25_CR4","series-title":"Lect Notes Comput Sci","volume-title":"Automatic verification of finite-state concurrent systems","author":"E. M. Clarke","year":"1994","unstructured":"E. M. Clarke. Automatic verification of finite-state concurrent systems. Lecture Notes in Computer Science, 815, 1994."},{"key":"25_CR5","doi-asserted-by":"crossref","unstructured":"R. Cleaveland, G. L\u00fcttgen, and V. Natarajan. Priority in process algebra. In J.A. Bergstra, A. Ponse, and S.A. Smolka, editors, Handbook of Process Algebra. Elsevier, 2000. To appear.","DOI":"10.1016\/B978-044482830-9\/50030-8"},{"key":"25_CR6","doi-asserted-by":"crossref","unstructured":"John Fiskio-Lasseter and Amr Sabry. Putting operational techniques to the test: A syntactic theory for behavioural Verilog. In The Third International Workshop on Higher Order Operational Techniques in Semantics (HOOTS'99), 1999.","DOI":"10.1016\/S1571-0661(05)80282-8"},{"key":"25_CR7","unstructured":"Mike Gordon, Thomas Kropf, and Dirk Hoffman. Semantics of the intemediate language IL. Technical Report D2.1c, PROSPER, 1999. available from \n                    http:\/\/www.cl.cam.ac.uk in \/users\/mjcg\/IL\/IL15.ps\n                    \n                  ."},{"key":"25_CR8","doi-asserted-by":"crossref","unstructured":"K. McMillan. Symbolic model checking: An approach to the state explosion problem. Kluwer Academic Publishers, 1993.","DOI":"10.1007\/978-1-4615-3190-6"},{"key":"25_CR9","unstructured":"Gordon J. Pace and Jifeng He. Formal reasoning with Verilog HDL. In Proceedings of the Workshop on Formal Techniques in Hardware and Hardware-like Systems, Marstrand, Sweden, June 1998."},{"key":"25_CR10","doi-asserted-by":"crossref","unstructured":"H. Sasaki. A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstract State Machine. In Proceedings of DATE\u201999 (Design, Automation and Test in Europe), ICM Munich, Germany, March 1999.","DOI":"10.1145\/307418.307520"},{"key":"25_CR11","volume-title":"IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language","author":"IEEE Computer Society.","year":"1996","unstructured":"IEEE Computer Society. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language. IEEE Computer Society Press, Piscataway, USA, 1996."},{"key":"25_CR12","doi-asserted-by":"crossref","unstructured":"P. F. Williams, A. Biere, E.M. Clarke, and A. Gupta. Combining decision diagrams and SAT procedures for efficient symbolic model checking. In CAV00, 2000.","DOI":"10.1007\/10722167_13"}],"container-title":["Lecture Notes in Computer Science","Formal Methods in Computer-Aided Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-40922-X_25","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,1,29]],"date-time":"2020-01-29T13:40:30Z","timestamp":1580305230000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-40922-X_25"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540412199","9783540409229"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/3-540-40922-x_25","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]},"assertion":[{"value":"18 June 2002","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}