{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:52:39Z","timestamp":1725490359738},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540679561"},{"type":"electronic","value":"9783540445203"}],"license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44520-x_135","type":"book-chapter","created":{"date-parts":[[2007,8,29]],"date-time":"2007-08-29T03:51:43Z","timestamp":1188359503000},"page":"960-964","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Two-Level Address Storage and Address Prediction"],"prefix":"10.1007","author":[{"given":"Enric","family":"Morancho","sequence":"first","affiliation":[]},{"given":"Jos\u00e9 Mar\u00eda","family":"Llaber\u00eda","sequence":"additional","affiliation":[]},{"given":"\u00c0ngel","family":"Oliv\u00e9","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2000,8,18]]},"reference":[{"key":"135_CR1","unstructured":"Alpha 21264 MicroProcessor Data Sheet. (1999). Compaq Computer Corporation."},{"key":"135_CR2","doi-asserted-by":"crossref","unstructured":"B. Black, B. Mueller, S. Postal, R. Rakvic, N. Utamaphethai and J.P. Shen. (1998). Load Execution Latency Reduction. In ICS-12, pp. 29\u201336","DOI":"10.1145\/277830.277842"},{"key":"135_CR3","doi-asserted-by":"crossref","unstructured":"M. Farrens and A. Park. (1991). Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. In ISCA-18, pp. 128\u2013137.","DOI":"10.1145\/115952.115966"},{"key":"135_CR4","doi-asserted-by":"crossref","unstructured":"J. Gonz\u00e1lez and A. Gonz\u00e1lez. (1997). Speculative Execution via Address Prediction and Data Prefetching. In ICS-11.","DOI":"10.1145\/263580.263631"},{"issue":"4","key":"135_CR5","doi-asserted-by":"publisher","first-page":"60","DOI":"10.1109\/40.710872","volume":"18","author":"B. Jacob","year":"1998","unstructured":"B. Jacob and T. Mudge. (1998). Virtual Memory in Contemporary Microprocessors. IEEE Micro, Vol 18(4), pp. 60\u201375.","journal-title":"IEEE Micro"},{"key":"135_CR6","doi-asserted-by":"crossref","unstructured":"M.H. Lipasti, C. B. Wilkerson and J.P. Shen. (1996). Value Locality and Load Value Prediction. In ASPLOS-7.","DOI":"10.1145\/237090.237173"},{"key":"135_CR7","doi-asserted-by":"crossref","unstructured":"E. Morancho, J.M. Llaber\u00eda and \u00c0. Oliv\u00e9. (1998). Split Last Address Predictor. In PACT\u201998.","DOI":"10.1109\/PACT.1998.727255"},{"key":"135_CR8","doi-asserted-by":"crossref","unstructured":"E. Morancho, J.M. Llaber\u00eda and \u00c0. Oliv\u00e9. (1999). Looking at History to Filter Allocations in Prediction Tables. In PACT99, pp. 314\u2013319","DOI":"10.1109\/PACT.1999.807577"},{"key":"135_CR9","unstructured":"E. Morancho, J.M. Llaber\u00eda and \u00c0. Oliv\u00e9. (1999). Two Level Address Storage and Address Prediction. Technical report UPC-DAC-99\/48."},{"key":"135_CR10","unstructured":"G. Reinman and B. Calder. (1998). Predictive Techniques for Aggresive Load Speculation. In MICRO-31."},{"key":"135_CR11","unstructured":"Y. Sazeides and J.E. Smith. (1996). The Predictability of Data Values. In MICRO-29."},{"key":"135_CR12","unstructured":"A. Seznec. (1994). Decoupled sectored caches: reconciliating low tag volume and low miss rate. In ISCA-21."},{"key":"135_CR13","doi-asserted-by":"crossref","unstructured":"H. Wang, T. Sung and Q. Yang. (1997). Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags. IEEE Transactions on Computers, 46(11).","DOI":"10.1109\/12.644293"}],"container-title":["Lecture Notes in Computer Science","Euro-Par 2000 Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44520-X_135","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,20]],"date-time":"2020-04-20T00:27:56Z","timestamp":1587342476000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44520-X_135"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540679561","9783540445203"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/3-540-44520-x_135","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]},"assertion":[{"value":"18 August 2000","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}