{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,23]],"date-time":"2025-01-23T11:40:09Z","timestamp":1737632409425,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540423287"},{"type":"electronic","value":"9783540445708"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2001]]},"DOI":"10.1007\/3-540-44570-6_1","type":"book-chapter","created":{"date-parts":[[2007,11,13]],"date-time":"2007-11-13T19:10:02Z","timestamp":1194981002000},"page":"1-14","source":"Crossref","is-referenced-by-count":0,"title":["A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro"],"prefix":"10.1007","author":[{"given":"Junji","family":"Ogawa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2001,9,5]]},"reference":[{"doi-asserted-by":"crossref","unstructured":"[MaiISCA\u201900] Ken Mai, et al., \u201cSmart Memories: A Modular Re-configurable Architecture,\u201d In proceedings of the 7th Annual International Symposium on Computer Architecture, pages 161\u2013171, June 2000.","key":"1_CR1","DOI":"10.1145\/339647.339673"},{"doi-asserted-by":"crossref","unstructured":"[PattersonMicro\u201997] David Patterson, et al., \u201cA Case for Intelligent RAM,\u201d IEEE Micro, pages 34\u201344, Mar.\/Apr. 1997.","key":"1_CR2","DOI":"10.1109\/40.592312"},{"doi-asserted-by":"crossref","unstructured":"[CrispMicro\u201997] Richard Crisp, \u201cDirect RAMBUS Technology,\u201d IEEE Micro, pages 18\u201328, Nov.\/Dec 1997.","key":"1_CR3","DOI":"10.1109\/40.641593"},{"doi-asserted-by":"crossref","unstructured":"[TakahashiISSCC\u201900] O. Takahashi, et al., \u201c1GHz Fully-Pipelined 3.7ns Address Access Time 8kx1024 Embedded DRAM Macro,\u201d In Digest of Technical Papers ISSCC 2000, Pages 396\u2013397, Feb. 2000.","key":"1_CR4","DOI":"10.1109\/ISSCC.2000.839831"},{"doi-asserted-by":"crossref","unstructured":"[WatanabeISSCC\u201999]_T. Watanabe, et al., \u201cAccess Optimizer to overcome the \u2018Future Walls of Embedded DRAMs\u2019 in the Era of Systems on Silicon,\u201d In Digest of Technical Papers ISSCC 1999, Pages 370\u2013371, Feb. 1999.","key":"1_CR5","DOI":"10.1109\/ISSCC.1999.759300"},{"doi-asserted-by":"crossref","unstructured":"[KimuraISSCC\u201999] T. Kimura, et al., \u201c64Mbit 6.8ns Random Row Access DRAM Macro for ASICs,\u201d In Digest of Technical Papers ISSCC 1999, pages 416\u2013417, Feb. 1999.","key":"1_CR6","DOI":"10.1109\/ISSCC.1999.759331"},{"issue":"11","key":"1_CR7","doi-asserted-by":"publisher","first-page":"1589","DOI":"10.1109\/4.799867","volume":"34","author":"Y. H. Yoon","year":"1999","unstructured":"[YoonJSSC\u201999] Hongil Yoon, et al., \u201cA 2.5-V, 333-Mb\/s\/pin, 1Gbit, Double-Data-Rate Synchronous DRAM,\u201d IEEE Journal of Solid-State Circuits, Vol.34No11, pages 1589\u20131597, Nov. 1999.","journal-title":"IEEE Journal of Solid-State Circuits"},{"doi-asserted-by":"crossref","unstructured":"[ManVLSI\u201996] Jin-Man Han, et al., \u201cSkew Minimization Techniques for 256-Mbit Synchronous DRAM and Beyond,\u201d 1996 Symposium on VLSI Circuits Digest of Technical Papers, pages 192\u2013193, June 1996.","key":"1_CR8","DOI":"10.1109\/VLSIC.1996.507767"},{"doi-asserted-by":"crossref","unstructured":"[OluktonISCA\u201999] K. Olukton, et al., \u201cImproving the performance of speculative Parallel Applications on the Hydra CMP,\u201d In proceedings of the 1999 ACM International Conference on Supercomputing, June 1999.","key":"1_CR9","DOI":"10.1145\/305138.305155"},{"doi-asserted-by":"crossref","unstructured":"[RixnerISCA\u201900] Scott Rixner, et al., \u201cMemory Access Scheduling,\u201d In proceeding of the 7th Annual International Symposium on Computer Architecture, pages 128\u2013138, June 2000.","key":"1_CR10","DOI":"10.1145\/339647.339668"},{"doi-asserted-by":"crossref","unstructured":"[Panda\u201999] Preeti R. Panda, N.D. Dutt, A. Nicolau, \u201cMemory Issues in Embedded System-On-Chip-Optimization and Exploration-,\u201d Kluwer Academic Publishers, ISBN 0-7893-8362-1, 1999.","key":"1_CR11","DOI":"10.1007\/978-1-4615-5107-2_1"},{"doi-asserted-by":"crossref","unstructured":"[RixnerISM\u201998] Scott Rixner, et al., \u201cA Bandwidth Efficient Architecture for Media Processing,\u201d In Proceedings of the 31st Annual International Symposium on Microarchitecture, pages 3\u201313, Nov.-Dec. 1998.","key":"1_CR12","DOI":"10.1109\/MICRO.1998.742118"},{"unstructured":"[RAMBUS-website] http:\/\/www.rambus.com\/developer\/quickfind_documents.html","key":"1_CR13"},{"unstructured":"[Mosys-data sheet] http:\/\/www.mosysinc.com\/prelease3\/ , MC80364K64, 64Kx64 PBSRAM.","key":"1_CR14"},{"unstructured":"[HorowitzSRC\u201999] Mark Horowitz, et al., \u201cThe Future of Wires,\u201d SRC White Paper: Interconnect Technology Beyond the Roadmap, 1999, ( http:\/\/www.src.org\/cgibin\/deliver.cgi\/sarawp.pdf?\/areas\/nis\/sarawp.pdf ).","key":"1_CR15"},{"doi-asserted-by":"crossref","unstructured":"[MukaiISSCC\u201900] Hideo. Mukai, et al., \u201cNew Architecture for Cost-Efficient High-Performance Multiple-Bank,\u201d In Digest of Technical Papers ISSCC 2000, Pages 400\u2013401, Feb.2000.","key":"1_CR16","DOI":"10.1109\/ISSCC.2000.839833"},{"doi-asserted-by":"crossref","unstructured":"[ParisISSCC\u201999] Lluis. Paris, et al., \u201cA 800MB\/s 72Mb SLDRAM with digitally-Calibrated DLL,\u201d In Digest of Technical Papers ISSCC 1999, Pages 414\u2013415, Feb. 1999.","key":"1_CR17","DOI":"10.1109\/ISSCC.1999.759329"},{"issue":"6","key":"1_CR18","doi-asserted-by":"publisher","first-page":"831","DOI":"10.1109\/4.766817","volume":"34","author":"G. J. C. Gealow","year":"1999","unstructured":"[GealowJSSC\u201999] Jeffrey C. Gealow, et al., \u201cA Pixel Parallel Image Processor Using Logic Pitch-Matched to Dynamic Memory,\u201d IEEE Journal of Solid-State Circuits, Vol.34No6, pages 831\u2013839, Nov. 1999.","journal-title":"IEEE Journal of Solid-State Circuits"}],"container-title":["Lecture Notes in Computer Science","Intelligent Memory Systems"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44570-6_1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,22]],"date-time":"2025-01-22T08:04:32Z","timestamp":1737533072000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44570-6_1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001]]},"ISBN":["9783540423287","9783540445708"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/3-540-44570-6_1","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2001]]}}}