{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,15]],"date-time":"2025-07-15T03:22:59Z","timestamp":1752549779411},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678991"},{"type":"electronic","value":"9783540446149"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_23","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T17:25:22Z","timestamp":1192901122000},"page":"201-210","source":"Crossref","is-referenced-by-count":2,"title":["Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards"],"prefix":"10.1007","author":[{"given":"Sushil Chandra","family":"Jain","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anshul","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shashi","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"key":"23_CR1","series-title":"Ph.D. thesis","volume-title":"Routing Architecture and Layout Synthesis for Multi-FPGA Systems","author":"M. A.S. Khalid","year":"1999","unstructured":"Mohammed A.S. Khalid, Routing Architecture and Layout Synthesis for Multi-FPGA Systems, Ph.D. thesis, University of Toronto, Department of Electrical and Computer Engineering, University of Toronto, 10 King\u2019s College Road, Toronto, Ontario Canada M5S 3G4, 1999."},{"key":"23_CR2","series-title":"Ph.D. thesis","volume-title":"Multi-FPGA Systems","author":"S. Hauck","year":"1995","unstructured":"Scott Hauck, Multi-FPGA Systems, Ph.D. thesis, University of Washington, Deptt of Comp Sc and Engg, Univ of Washington, Seatle, 1995."},{"issue":"6","key":"23_CR3","doi-asserted-by":"crossref","first-page":"609","DOI":"10.1109\/43.640619","volume":"16","author":"J. Babb","year":"1997","unstructured":"J. Babb et al, \u201cLogic Emulation with Virtual Wires,\u201d IEEE Trans. on CAD, vol. 16, no. 6, pp. 609\u2013626, June 1997.","journal-title":"IEEE Trans. on CAD"},{"key":"23_CR4","doi-asserted-by":"crossref","unstructured":"K. Roy-Neogi and C. Sechan, \u201cMultiple-FPGA Partitioning with Performance Optimization,\u201d International Symposium on FPGAs, pp. 146\u2013152, 1995.","DOI":"10.1109\/FPGA.1995.242148"},{"key":"23_CR5","doi-asserted-by":"crossref","unstructured":"Panos M. Pardalos, Franz Rendl and Henry Wolkowicz, \u201cThe Quadratic Assignment Problem: A Survey and Recent Developments,\u201d American Mathematical Society Publications \u2014 DIMACS Volume Series, vol. 16, 1994.","DOI":"10.1090\/dimacs\/016\/01"},{"key":"23_CR6","unstructured":"S. Yang, \u201cLogic Synthesis and Optimization Benchmarks User Guide Version 3.0,\u201d Microelectronics Centre of North Carolina, January 1991."},{"issue":"1","key":"23_CR7","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/43.273754","volume":"13","author":"J. Cong","year":"1994","unstructured":"Cong, J. and Y. Ding, \u201cFlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,\u201d IEEE Trans. on Computer-Aided Design, vol. 13, no. 1, pp. 1\u201312, 1994.","journal-title":"IEEE Trans. on Computer-Aided Design"},{"key":"23_CR8","doi-asserted-by":"crossref","unstructured":"M. Hutton et al, \u201cCharacterization and Parameterized Random Generation of Digital Circuits,\u201d Proceedings of the DAC, Las Vegas, pp. 94\u201399, 1996.","DOI":"10.1145\/240518.240537"},{"key":"23_CR9","volume-title":"hMETIS* \u2014 A Hypergraph Partitioning Package Version 1.5.3","author":"G. Karypis","year":"1998","unstructured":"George Karypis and Vipin Kumar, \u201chMETIS* \u2014 A Hypergraph Partitioning Package Version 1.5.3,\u201d Computer Science Dept.,University of Minnesota, Minnepolis, MN 55455, 1998."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_23","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T22:06:23Z","timestamp":1556921183000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_23"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_23","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}