{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T14:16:48Z","timestamp":1742393808829,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678991"},{"type":"electronic","value":"9783540446149"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_39","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T17:25:22Z","timestamp":1192901122000},"page":"361-370","source":"Crossref","is-referenced-by-count":1,"title":["A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems"],"prefix":"10.1007","author":[{"given":"Xue-jie","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kam-wing","family":"Ng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Luk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"key":"39_CR1","doi-asserted-by":"crossref","unstructured":"J. Villasenor, B. Schoner, K. Chia, C. Zapata and B. Mangione-Smith: Configurable Computing Solutions for Automatic Target Recognition, Proc. FCCM\u201996, IEEE Computer Society Press, 1996, pp. 70\u201379.","DOI":"10.1109\/FPGA.1996.564749"},{"key":"39_CR2","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1007\/BF00936947","volume":"12","author":"J.G. Eldrege","year":"1996","unstructured":"J.G. Eldrege and B.L. Hutchings: Run-time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs, J. VLSI Signal Processing, Vol. 12, 1996, pp. 67\u201386.","journal-title":"J. VLSI Signal Processing"},{"key":"39_CR3","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"419","DOI":"10.1007\/3-540-60294-1_136","volume-title":"Field-Programmable Logic and Aplications","author":"B.L. Hutchings","year":"1995","unstructured":"B.L. Hutchings and M.J. Wirthlin: Implementation Approaches for Reconfigurable Logic Applications, Field-Programmable Logic and Aplications, LNCS 975, Springer-Verlag, 1995, pp. 419\u2013428."},{"issue":"1","key":"39_CR4","doi-asserted-by":"publisher","first-page":"2","DOI":"10.1145\/250243.250245","volume":"2","author":"Y.L. Lin","year":"1997","unstructured":"Y.L. Lin: Recent Developments in High-level Synthesis, ACM Trans. on Design of Electronic Systems, Vol. 2, No. 1, January 1997, pp. 2\u201321.","journal-title":"ACM Trans. on Design of Electronic Systems"},{"key":"39_CR5","unstructured":"M. Kaul, R. Vemuri, S. Govindarajan and I. Ouaiss: An Automated Temporal Partitioning Tool for a Class of DSP Application, Proc. PACT\u201998, 1998."},{"key":"39_CR6","doi-asserted-by":"crossref","unstructured":"M. Kaul and R. Vemuri: Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-time Reconfigured Designs, Proc. Data\u201999, 1999.","DOI":"10.1145\/307418.307490"},{"issue":"6","key":"39_CR7","doi-asserted-by":"publisher","first-page":"579","DOI":"10.1109\/12.773795","volume":"48","author":"K.M.G. Purna","year":"1999","unstructured":"K.M.G. Purna and D. Bhatia: Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers, IEEE Trans. on Computers, Vol. 48, No. 6, 1999, pp. 579\u2013590.","journal-title":"IEEE Trans. on Computers"},{"key":"39_CR8","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"290","DOI":"10.1007\/3-540-61730-2_31","volume-title":"Field-Programmable Logic and Applications","author":"M. Vasilko","year":"1996","unstructured":"M. Vasilko and D. Ait-Boudaoud: Architectural Synthesis Techniques for Dynamically Reconfigurable Logic, Field-Programmable Logic and Applications, LNCS 1142, Springer-Verlag, 1996, pp. 290\u2013296."},{"key":"39_CR9","first-page":"14","volume-title":"Proc. 5th Annual Australasian Conference on Parallel And Real-Time Systems (PART\u201998)","author":"K.W. Ng","year":"1998","unstructured":"K.W. Ng, X.J. Zhang and G.H. Young: Design Representation for Dynamically Reconfigurable Systems, Proc. 5th Annual Australasian Conference on Parallel And Real-Time Systems (PART\u201998), Springer-Verlag (Singapore), 1998, pp. 14\u201323."},{"key":"39_CR10","unstructured":"X.J. Zhang, K.W. Ng and G.H. Young: High-level Synthesis Using Genetic Algorithms for Dynamically Reconfigurable FPGAs, Proc. 23rd Euromicro Conference (EUROMICRO\u2019 97), 1997."},{"key":"39_CR11","series-title":"Lect Notes Comput Sci","first-page":"932","volume-title":"Parallel and Distributed Processing","author":"K.W. Ng","year":"2000","unstructured":"K.W. Ng and X.J. Zhang: Module Allocation for Dynamically Reconfigurable Systems, Parallel and Distributed Processing, LNCS1800, Springer-Verlag, 2000, pp. 932\u2013940."},{"key":"39_CR12","doi-asserted-by":"crossref","unstructured":"W. Luk, N. Shirazi and P.Y.K. Cheung: Modelling and Optimizing Run-Time Reconfigurable Systems, Proc. FCCM\u201996, IEEE Computer Society Press, 1996, pp. 167\u2013176.","DOI":"10.1109\/FPGA.1996.564815"},{"key":"39_CR13","doi-asserted-by":"crossref","unstructured":"W. Luk, N. Shirazi and P.Y.K. Cheung: Compilation Tools for Run-Time Reconfigurable Designs, Proc. FCCM\u201997, IEEE Computer Society Press, 1997, pp. 56\u201365.","DOI":"10.1109\/FPGA.1997.624605"},{"key":"39_CR14","doi-asserted-by":"crossref","unstructured":"N. Shirazi, W. Luk and P.Y.K. Cheung: Automating Production of Run-Time Reconfigurable Designs, Proc. FCCM\u201998, IEEE Computer Society Press, 1998, pp. 147\u2013156.","DOI":"10.1109\/FPGA.1998.707892"},{"key":"39_CR15","doi-asserted-by":"crossref","unstructured":"J. Jaffar and M.J. Maher: Constraint Logic Programming: A Survey, The Journal of Logic Programming, 1994.","DOI":"10.1016\/0743-1066(94)90033-7"},{"key":"39_CR16","doi-asserted-by":"crossref","unstructured":"K. Marriot and P.J. Stuckey: Programming with Constraints \u2014 An Introduction, The MIT Press, 1998.","DOI":"10.7551\/mitpress\/5625.001.0001"},{"key":"39_CR17","unstructured":"CHIP, System Documentation, COSYTEC, 1996."},{"key":"39_CR18","unstructured":"A. Aggoun and N. Beldiceanu: Overview of the CHIP Compiler System, Proc. 8th International Conference on Logic Programming, 1991, pp. 775\u2013789."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_39","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T19:59:30Z","timestamp":1737489570000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_39"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_39","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}