{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,4]],"date-time":"2026-04-04T18:12:49Z","timestamp":1775326369350,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540678991","type":"print"},{"value":"9783540446149","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_58","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T13:25:22Z","timestamp":1192886722000},"page":"535-544","source":"Crossref","is-referenced-by-count":19,"title":["Balancing Logic Utilization and Area Efficiency in FPGAs"],"prefix":"10.1007","author":[{"given":"Russell","family":"Tessier","sequence":"first","affiliation":[]},{"given":"Heather","family":"Giza","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"key":"58_CR1","unstructured":"Prep Benchmark Suite. http:\/\/www.prep.org , 1999."},{"key":"58_CR2","unstructured":"Altera Data Book. Altera Corporation, 2000."},{"key":"58_CR3","unstructured":"Xilinx Corporation. http:\/\/www.xilinx.com , 2000."},{"key":"58_CR4","doi-asserted-by":"crossref","unstructured":"A. Agarwal and D. Lewis. Routing Architectures for Hierarchical Field Programmable Gate Arrays. In Proceedings IEEE International Conference on Computer Design, Oct. 1994.","DOI":"10.1109\/ICCD.1994.331954"},{"key":"58_CR5","doi-asserted-by":"crossref","unstructured":"J. Babb, M. Frank, V. Lee, E. Waingold, and R. Barua. The RAW Benchmark Suite: Computation Structures for General Purpose Computing. In Proceedings, IEEE Workshop on FPGA-based Custom Computing Machines, Napa, Ca, Apr. 1997.","DOI":"10.1109\/FPGA.1997.624613"},{"key":"58_CR6","unstructured":"V. Betz and J. Rose. On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs. University of Toronto Department of Electrical Engineering, Technical Report, June 1996."},{"key":"58_CR7","doi-asserted-by":"crossref","unstructured":"V. Betz and J. Rose. Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size. In Proceedings, IEEE Custom Integrated Circuits Conference, pages 551\u2013554, 1997.","DOI":"10.1109\/CICC.1997.606687"},{"key":"58_CR8","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5145-4","volume-title":"Architecture and CAD for Deep-Submicron FPGAs","author":"V. Betz","year":"1999","unstructured":"V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Boston, Ma, 1999."},{"key":"58_CR9","doi-asserted-by":"crossref","unstructured":"G. Borriello, C. Ebeling, S. Hauck, and S. Burns. The Triptych FPGA Architecture. IEEE Transactions on VLSI, pages 491\u2013501, Dec. 1995.","DOI":"10.1109\/92.475968"},{"key":"58_CR10","doi-asserted-by":"crossref","unstructured":"A. Dehon. Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don\u2019t really want 100% LUT utilization). In 7th International Workshop on Field-Programmable Gate Arrays, Monterey, Ca, Feb. 1999.","DOI":"10.1145\/296399.296431"},{"key":"58_CR11","unstructured":"C. M. Fiduccia and R. M. Mattheyses. A Linear Time Heuristic for Improving Network Partitions. In Design Automation Conference, May 1984."},{"key":"58_CR12","doi-asserted-by":"crossref","unstructured":"B. Landman and R. Russo. On a Pin Versus Block Relationship For Partitions of Logic Graphs. IEEE Transactions on Computers, C-20(12), Dec. 1971.","DOI":"10.1109\/T-C.1971.223159"},{"key":"58_CR13","doi-asserted-by":"crossref","unstructured":"A. Marquardt, V. Betz, and J. Rose. Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. In International Symposium on Field Programmable Gate Arrays, Monterey, Ca., Feb. 1998.","DOI":"10.1145\/296399.296426"},{"key":"58_CR14","unstructured":"R. Tessier. Fast Place and Route Approaches for FPGAs: Chapter 6. PhD thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1999. available at http:\/\/www.ecs.umass.edu\/ece\/tessier\/tessier.html ."},{"key":"58_CR15","doi-asserted-by":"crossref","unstructured":"R. Tessier and H. Giza. Balancing Logic Utilization and Area Efficiency in FPGAs. University of Massachusetts Department of Electrical and Computer Engineering, Technical Report TR-CSE-00-5, June 2000.","DOI":"10.1007\/3-540-44614-1_58"},{"key":"58_CR16","doi-asserted-by":"crossref","unstructured":"W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. Dehon. HSRA: High-Speed Synchronous Reconfigurable Array. In 7th International Workshop on Field-Programmable Gate Arrays, Monterey, Ca, Feb. 1999.","DOI":"10.1145\/296399.296442"},{"key":"58_CR17","unstructured":"S. Yang. Logic Synthesis and Optimization Benchmarks. Microelectronics Centre of North Carolina Tech. Report, 1991."}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_58","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T18:06:12Z","timestamp":1556906772000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_58"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_58","relation":{},"ISSN":["0302-9743"],"issn-type":[{"value":"0302-9743","type":"print"}],"subject":[],"published":{"date-parts":[[2000]]}}}