{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T20:40:01Z","timestamp":1737492001265,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540678991"},{"type":"electronic","value":"9783540446149"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2000]]},"DOI":"10.1007\/3-540-44614-1_61","type":"book-chapter","created":{"date-parts":[[2007,10,20]],"date-time":"2007-10-20T17:25:22Z","timestamp":1192901122000},"page":"565-574","source":"Crossref","is-referenced-by-count":0,"title":["Optimization of Run-Time Reconfigurable Embedded Systems"],"prefix":"10.1007","author":[{"given":"Michael","family":"Eisenring","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Platzner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2002,4,12]]},"reference":[{"doi-asserted-by":"crossref","unstructured":"J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In IEEE Workshop on FPGA-based Custom Computing Machines, pages 142\u2013151, Napa, CA, April 1993.","key":"61_CR1","DOI":"10.1109\/FPGA.1993.279469"},{"issue":"6","key":"61_CR2","doi-asserted-by":"crossref","first-page":"609","DOI":"10.1109\/43.640619","volume":"16","author":"J. Babb","year":"1997","unstructured":"J. Babb, R. Tessier, M. Dahl, S. Hanono, D. Hoki, and A. Agarwal. Logic emulation with virtual wires. IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, 16(6):609\u2013626, June 1997.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems"},{"key":"61_CR3","series-title":"Lect Notes Comput Sci","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1007\/978-3-540-48302-1_18","volume-title":"9th International Workshop on Field-Programmable Logic and Applications, FPL\u201999","author":"K. Chatha","year":"1999","unstructured":"K. Chatha and R. Vemuri. Hardware-Software Codesign for Dynamically Reconfigurable Architectures. In 9th International Workshop on Field-Programmable Logic and Applications, FPL\u201999, Lecture Notes in Computer Science, 1673, pages 175\u2013184, Glasgow, UK, August\/September 1999."},{"doi-asserted-by":"crossref","unstructured":"R. Dick and N. Jha. CORDS: Hardware-Software Co-Synthesis of Reconfigurable Real-Time Distributed Embedded Systems. In IEEE\/ACM International Conference on Computer-Aided Design, pages 62\u201368, 8\u201312 November 1998.","key":"61_CR4","DOI":"10.1145\/288548.288561"},{"key":"61_CR5","volume-title":"The Second International Workshop on Engineering of Reconfigurable Hardware\/Software Objects, ENREGLE 2000","author":"M. Eisenring","year":"2000","unstructured":"M. Eisenring and M. Platzner. An Implementation Framework for Run-time Reconfigurable Systems. In The Second International Workshop on Engineering of Reconfigurable Hardware\/Software Objects, ENREGLE 2000, Monte Carlo Resort, Las Vegas, Nevada, USA, June 26\u201329 2000."},{"doi-asserted-by":"crossref","unstructured":"M. Eisenring and M. Platzner. Synthesis of Interfaces and Communication in Recon.gurable Embedded Systems. To appear in IEE Proceedings \u2014 Computers and Digital Techniques, 2000.","key":"61_CR6","DOI":"10.1049\/ip-cdt:20000496"},{"doi-asserted-by":"crossref","unstructured":"M. Eisenring, M. Platzner, and L. Thiele. Communication Synthesis for Recon.gurable Embedded Systems. In 9th International Workshop on Field-Programmable Logic and Applications, pages 205\u2013214, Glasgow, UK, August\/September 1999.","key":"61_CR7","DOI":"10.1007\/978-3-540-48302-1_21"},{"issue":"3","key":"61_CR8","doi-asserted-by":"crossref","first-page":"159","DOI":"10.1016\/0141-9331(95)01073-4","volume":"20","author":"R. Ernst","year":"1996","unstructured":"R. Ernst, J. Henkel, T. Benner, W. Ye, U. Holtmann, and D. Herrmann. The COSYMA environment for hardware\/software cosynthesis of small embedded systems. Microprocessors and Microsystems, 20(3):159\u2013166, May 1996.","journal-title":"Microprocessors and Microsystems"},{"doi-asserted-by":"crossref","unstructured":"B. Hutchings and M. Wirthlin. Implementation Approaches for Reconfigurable Logic Applications. In International Workshop on Field-Programmable Logic and Applications, pages 419\u2013428, 1995.","key":"61_CR9","DOI":"10.1007\/3-540-60294-1_136"},{"doi-asserted-by":"crossref","unstructured":"A. Kirschbaum and M. Glesner. Rapid Prototyping of Communication Architectures. In 8th IEEE Int. Workshop on Rapid System Prototyping, pages 136\u2013141, June 24\u201326 1997, Chapel Hill, North Carolina.","key":"61_CR10","DOI":"10.1109\/IWRSP.1997.618889"},{"unstructured":"M. O\u2019Nils and A. Jantsch. Communication in Hardware\/Software Embedded Systems \u2014 A Taxonomy and Problem Formulation. In 15th NORCHIP Seminar, Copenhagen, Denmark, pages 67\u201374, November 1997.","key":"61_CR11"},{"doi-asserted-by":"crossref","unstructured":"R. Ortega and G. Borriello. Communication Synthesis for Distributed Embedded Systems. In IEEE\/ACM Int\u2019l Conf. on Computer-Aided Design, pages 437\u2013444, San Jose, CA, November 1998.","key":"61_CR12","DOI":"10.21236\/ADA416530"},{"issue":"6","key":"61_CR13","doi-asserted-by":"crossref","first-page":"556","DOI":"10.1109\/12.773795","volume":"48","author":"K. Purna","year":"1999","unstructured":"K. Purna and D. Bhatia. Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Transactions on Computers, 48(6):556\u2013564, June 1999.","journal-title":"IEEE Transactions on Computers"},{"issue":"6","key":"61_CR14","doi-asserted-by":"crossref","first-page":"556","DOI":"10.1109\/12.773792","volume":"48","author":"E. Sanchez","year":"1999","unstructured":"E. Sanchez, M. Sipper, J. Haenni, J. Beuchat, A. Stauffer, and A. Perez-Uribe. Static and Dynamic Configurable Systems. IEEE Transactions on Computers, 48(6):556\u2013564, June 1999.","journal-title":"IEEE Transactions on Computers"}],"container-title":["Lecture Notes in Computer Science","Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/3-540-44614-1_61","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T19:59:17Z","timestamp":1737489557000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/3-540-44614-1_61"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000]]},"ISBN":["9783540678991","9783540446149"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/3-540-44614-1_61","relation":{},"ISSN":["0302-9743"],"issn-type":[{"type":"print","value":"0302-9743"}],"subject":[],"published":{"date-parts":[[2000]]}}}